Simplified clocked DRAM with a fast command input

Details Simplified clocked DRAM with a fast command input Simplified clocked DRAM with a fast command input

1996-02-29

1998-05-05

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

36518903, G06F 1202

Patent

active

057490864

ABSTRACT:
A synchronous memory device is described which is a relatively uncomplicated modification of an asynchronous DRAM such as a Burst Extended Data Out (BEDO) DRAM. The memory device receives the system clock signal, which provides many of those functions associated with the well known command signal CAS in asynchronous DRAMs. Chip and row select functions are controlled by the well known command signal RAS. Novel command signals CMND0 and CMND1 are supplied in place of the well known WE and OE command signals. The novel command signals are sampled at RAS time, at which time distinct combinations of the logic values of CMND0 and CMND1 represent distinct operating mode commands, such as Read, Write and Refresh. At each positive system clock edge following RAS time, the distinct combinations of the logic values of CMND0 and CMND1 represent distinct commands such as NOP, Switch Mode, and Latch Address. Full write command interrupt and/or byte-write capability can be provided, as desired.

REFERENCES:
patent: 4734880 (1988-03-01), Collins
patent: 5457659 (1995-10-01), Schaefer
patent: 5467314 (1995-11-01), Miyazawa
patent: 5511024 (1996-04-01), Ware
patent: 5521879 (1996-05-01), Takasugi
patent: 5544124 (1996-08-01), Zagar
patent: 5566119 (1996-10-01), Matano
1996 DRAM Data Book Micro Technology Inc, pp. 3-8-3-13, 1995.

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