Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-02-18
2004-03-09
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
06704903
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to electronic devices, and, more particularly, to low-complexity partial response detectors.
Magnetic recording systems for digital data storage may have a functional structure as illustrated in FIG.
1
. Briefly, for a write of data to storage, data bits typically first receive error correction encoding (such as Reed-Solomon); this coding aims to correct errors generated in the write-read process and which escape correction by the detection method of the read process. Further, interleaving blocks of error corrected encoded bits helps correct bursts of errors by spreading the errors over many blocks. Next, the error correction encoded bits are modulation (channel) coded (such as runlength-limited coding); the modulation coding helps read timing recovery. A further precoding may help intersymbol interference decoding. Then the modulation coded bits modulate the polarity of the write current in a read/write head over the magnetic media (e.g., a spinning disk) to set the magnetization directions of domains in the magnetic media. The pattern of magnetization directions is the stored data.
The read process begins with sensing the domain magnetization directions by voltages induced in the read/write head. After amplification the sensed voltages drive clocked analog-to-digital converters to yield a stream of digital samples. Noise in the read sensing, amplification, and conversion generates errors in the stream of digital samples. A detector (such as a peak detector or a Viterbi maximum likelihood detector) recovers the modulation encoded bits from the stream of digital samples. The modulation decoder then converts the coded bits to the error corrected bits, and lastly, the deinterleaver and error correction decoder corrects errors and recovers the data bits.
For partial response signaling various classes of frequency response for the signal channel prior to detection have been defined; and the class IV response appears particularly suitable for magnetic recording due to pulse shapes requiring minimal equalization. The partial response class IV channel is defined by a channel transfer function polynomial of the form (1−D)(1+D)
N
where N is a positive integer and D is a one period delay.
FIGS. 2
a
-
2
c
shows the pulse shapes for N=1, 2, and 3; the corresponding pulses are termed PR4, EPR4, and E
2
PR4 (or EEPR4), respectively. Thus an (E)PR4 sensed voltage consists of a sequence of overlapping (E)PR4 pulses spaced one period apart and with positive, negative, or zero amplitudes depending upon the corresponding transitions of magnetization domain orientations. The sampling of the (E)PR4 sensed voltage yields the digital stream input to the detector, typically a sequence detector such as a maximum likelihood Viterbi decoder. Higher storage densities on a magnetic disk require more samples per induced pulse and consequent more overlap, and thus the higher order polynomial transfer functions are used. For example, storage densities of about 3 bits per pulse halfwidth would use E
2
PR4 which has four nonzero samples per pulse; see
FIG. 2
c
. The demand for high density originates with small, portable devices such as notebook computers.
However, higher order polynomial transfer functions require more complex Viterbi detectors because the number of states equals 2N+1 and thus the corresponding number of computations and the time to perform the computations increases rapidly. But high complexity implies high power consumption and slow execution, and this contradicts the requirements of notebook computers and their battery-based power supplies.
Known methods for reducing the complexity of a Viterbi detector include (i) reducing the number of accessible states by selection of modulation coding constraints and (ii) dynamically changing the add-compare-select (ACS) units of a typical Viterbi detector implementation from association with a single state to multiple states. See for example the background of U.S. Pat. No. 5,291,499.
Conway, A New Target Response with Parity Coding for High Density Magnetic Recording Channels, 34 IEEE Tr. Mag.2382 (1998), uses a single parity bit for post-Viterbi-detector processing to correct for occurrences of the dominant error patterns in a proposed system with an ideal response polynomial (1−D2)(2+2D+D2).
Siegel et al, Exact Bounds for Viterbi Detector Path Metric Differences, IEEE ICASSP 1991, pp. 1093-1096, generate upper and lower bounds on the differences of path metrics for trellis states.
SUMMARY OF THE INVENTION
The present invention provides a simplified computation for sequence detectors by use of minimal precision branch metrics plus approximations to quadratics to limit computation.
This has the advantages of faster and lower complexity Viterbi detectors.
REFERENCES:
patent: 5291499 (1994-03-01), Behrens et al.
patent: 5604724 (1997-02-01), Shiokawa
Conway, A New Target Response with Parity Coding for High Density Magnetic Recording Channels, IEEE, p. 2382-2386, 1998.*
Siegel et al., Exact Bounds for Viterbi Detector PAth MEtric Differences, IEEE, p. 1093-1096, 1991.*
Fitzpatrick, A Reduced Complexity EPR4 Post-Processor, IEEE, p. 135-140, Jan. 1998.*
Champlin et al., Non-Linear MAP Estimation using a Continuous-state Viterbi Algorithm, IEEE, p. 3703-3708, 1992.*
Paaske et al., High speed Viterbi decoder architecture, Jun. 1998, First ESA Workshop on Tracking, Telemetry and Command Systems, p. 1 to 8.
Chiu James Kar Shing
Fu Leo Ki Chun
Leung Michael Ming Tak
Nikolic Borivoje
Brady W. James
Chase Shelly A
Chung Phung M.
Hoel Carlton H.
Telecky , Jr. Frederick J.
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