Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2000-06-16
2002-03-05
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S083000, C326S057000
Reexamination Certificate
active
06353333
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of integrated circuits, and more specifically to digital logic input/output terminal circuits for interfacing logic circuits with other integrated circuit chips having more than one power supply level.
2. Related Art
When two digital logic devices having different power supply levels are coupled together, an interface circuit is generally required to prevent damage to transistors in the device having the lower power supply level. The interface circuit should also minimize leakage current and prevent latch-up.
For a given power supply voltage, the electric field strength, i.e. the change in voltage per unit length, that transistors are exposed to increases as the size of the transistors is reduced. Digital semiconductor devices have typically been powered by 5V supplies. The maximum electric field tolerance can be a limiting factor on the minimum transistor size. For example, a typical maximum gate oxide field strength for silicon dioxide gates is about 3 megavolts per centimeter. High electric fields inside a transistor can reduce the mean time to failure, and can destroy transistors when an electric field exceeds the breakdown value for a given material in a transistor, such as the gate oxide in CMOS devices.
To reduce the minimum transistor size imposed by the electric field, certain types of digital logic devices including CMOS devices are now powered with a 3.3V supply rather than a 5V supply. However, these 3.3V digital logic devices must often be connected to logic devices that operate with 5V supplies, such as, for example, TTL devices. Absent some form of protection, the 5V TTL signals can damage the 3.3V digital logic devices.
Programmable devices typically include pins that can be used for input or output signals depending upon how the device is programmed. These pins are called I/O pins or I/O terminals. An interface structure must be provided between the I/O pins and the internal portions of the programmable device. The interface structure operates in two modes: input pin mode (receive mode) and output pin mode (transmit mode). The interface structure receives a data-out signal from the internal portions of the programmable device. In transmit mode, the interface structure buffers the data-out signal and applies it to the I/O pin. The interface structure also provides a data-in signal to the internal portions of the programmable device. In receive mode, the interface structure places the output buffer into a tristate mode, disconnecting it from the I/O pin so that an input signal applied by an external source to the I/O pin does not conflict with the data-out signal. The input signal is then typically buffered to generate the data-in signal.
A 3.3V device can safely drive its own I/O pin during transmit mode. However, when the I/O pin of a 3.3V device is being driven by a neighboring 5V device, the 3.3V device must include protection circuits attached to the I/O pin. One prior art approach to protecting 3.3V digital logic circuits is to provide diodes at the power supply of the 3.3V device to limit the maximum voltage at the I/O pin common to the low and high voltage devices. In these devices when an external voltage is applied to an I/O pin that is sufficiently greater than the power supply voltage, the power supply diode turns on and draws current. This approach has a drawback of creating large leakage currents and increasing the power dissipation. Other approaches to providing an interface between digital logic devices with different voltage tolerance levels suffer from a variety of drawbacks. Some require a 5V power supply, others reduce the noise immunity of the circuit and increase the vulnerability of the circuit to latch-up, and still others require costly fabrication processes to produce a plurality of types of transistors of the same polarity with different threshold levels. Thus, an improved low voltage I/O circuit with a high voltage tolerance that avoids these and other prior art problems is needed.
SUMMARY OF THE INVENTION
The present invention provides a low voltage interface circuit with a high voltage tolerance. The present invention enables devices with different power supply levels to be efficiently coupled together without damage to the circuits of the low voltage device and without significant leakage current. By minimizing the gate oxide voltage drop in any one transistor, the present invention allows a single thinner gate oxide to be used in the interface circuit. Yet the same process technology can be used for the interface circuit as is used for the rest of the device, so manufacturing cost is kept low.
An interface circuit in accordance with the present invention comprises an impedance control circuit, an output buffer, an input buffer, an isolation circuit, and a pullup protection circuit. The circuit operates in two modes: input and output. Setting a tristate terminal to a low logic level places the interface circuit into a transmit or output mode and enables the output buffer. In transmit mode, the logic level at a data terminal is transmitted to an I/O pad. An embodiment of the present invention provides a buffered data path from the data terminal to the I/O pad. Setting the tristate terminal to a high logic level places the interface circuit into a receive or input mode and disables the output buffer.
When a high voltage (i.e., higher than the internal voltage of the interface circuit) is applied to the I/O pad, two problems can arise. First, the high voltage can create a damaging voltage potential across the gate oxides of transistors in the interface circuit, such as the pulldown transistor in the output buffer. Second, the high voltage can cause reverse current flow into the positive supply voltage of the interface circuit, for example through the pullup transistor of the output buffer.
Therefore, in accordance with the present invention, the output buffer includes an isolation transistor in series with the pulldown transistor to prevent excessive voltage across the gate oxide of the pulldown transistor. Also, the pullup protection circuit drives the gate of the pullup transistor to the high I/O pad voltage to ensure that no current flows to the positive supply voltage. Finally, the isolation circuit couples the high I/O pad voltage to the body (well) of the pullup transistor to prevent leakage current through parasitic diodes formed by the pullup transistor. In this manner, the present invention protects the interface circuit transistors from damage by high voltages at the I/O pad and avoids the large leakage currents of prior art circuits that have forward bias diodes at the power supply of the lower voltage circuit.
In a 3.3 volt circuit tolerant to 5.5 volt input signals, voltage drops greater than 3.6V (3.3V+10%) at a single transistor are prevented. In the input mode, when the externally applied voltage at the I/O pad is sufficiently below the positive supply voltage of the interface circuit, the isolation circuit drives the well voltage to approximately the positive supply voltage (e.g., 3.3V) and reverse biases the parasitic diode associated with the well, thereby ensuring that the well stays sufficiently biased and thus protecting the internal gate oxides from voltage differences greater than 3.6V. The interface circuit of the present invention can be used to couple circuits that have different power supply and logic levels as long as the ratio of voltage levels is not greater than 2:1. For example, the present invention can be used in a semiconductor device with a 2.5V power supply to couple it to a device with a 3.3V power supply.
The present invention will be more fully understood in view of the following description and drawings.
REFERENCES:
patent: 5451889 (1995-09-01), Heim et al.
patent: 5532621 (1996-07-01), Kobayashi et al.
patent: 5635861 (1997-06-01), Chan et al.
patent: 5933025 (1999-08-01), Nance et al.
patent: 6175952 (2001-01-01), Patel et al.
Curd Derek R.
Nguyen Hy V.
Bever Hoffman & Harms LLP
Harms Jeanette S.
Le Don Phu
Tokar Michael
Xilinx , Inc.
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