Simple and high speed BICMOS tristate buffer circuit

Details Simple and high speed BICMOS tristate buffer circuit Simple and high speed BICMOS tristate buffer circuit

1994-03-30

1995-03-14

Hudspeth, David R.

Electronic digital logic circuitry

Reliability

326 56, 326110, H03K 19003

Patent

active

053980000

ABSTRACT:
A simple and high speed BiCMOS tristate buffer circuit includes a first transistor coupled to a power supply and a first node. The first transistor has a control terminal coupled to receive a first signal. A second transistor is coupled to the first node and ground. The second transistor has a control terminal coupled to receive a second signal. A first bipolar transistor has a base coupled to the first node, a collector coupled to the power supply, and an emitter coupled to an output node of the circuit. A third transistor is coupled to the output node and the ground. The third transistor has a control terminal coupled to receive the second signal. A switching circuit is coupled to the first node and the output node for connecting the first node to the output node when the first and second signals turn off the first, second, and third transistors such that the output node assumes an open circuit condition. The switching circuit is controlled by a third signal. The first, second, and third signals control the first and second transistors and the switching circuit to provide a path from the first input signal to the output node containing only one inverter, one P-channel transistor, and one bipolar transistor. This path allows the buffer circuit to have high switching speed and simple circuit structure. A logic circuit is coupled to receive a first input signal and a second input signal for generating the first, second, and third signals.

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