Similarity-driven synthesis for equivalence checking of...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000, C716S030000

Reexamination Certificate

active

07137084

ABSTRACT:
A method for modeling a circuit design includes synthesizing the circuit design to create a first gate-level representation of the circuit design. The method also includes analyzing a second gate-level representation of the circuit design to learn architecture information, and resynthesizing the first gate-level representation of the circuit design to incorporate the learned architecture information from the second gate-level representation of the circuit design. A computer-readable storage medium has stored thereon computer instructions that, when executed by a computer, cause the computer to synthesize a circuit design to create a first gate-level representation of the circuit design. The computer instructions also cause the computer to analyze a second gate-level representation of the circuit design to learn architecture information, and resynthesize the first gate-level representation of the circuit design to incorporate the learned architecture information from the second gate-level representation of the circuit design.

REFERENCES:
patent: 5519627 (1996-05-01), Mahmood et al.
patent: 5841663 (1998-11-01), Sharma et al.
patent: 6148436 (2000-11-01), Wohl
patent: 6163876 (2000-12-01), Ashar et al.
patent: 6336206 (2002-01-01), Lockyear
patent: 6378112 (2002-04-01), Martin et al.
patent: 6490717 (2002-12-01), Pedersen et al.
patent: 6530073 (2003-03-01), Morgan
patent: 6611947 (2003-08-01), Higgins et al.
patent: 2001/0010090 (2001-07-01), Boyle et al.
Brand, D., “Verification of Large Synthesized Designs,” Proc. 1993 IEEE Int'l. Conf. on CAD, Nov. 1993, pp. 534-537.
Burch, J.R. et al., “Symbolic Model Checking for Sequential Circuit Verification,” IEEE Transactions on, Apr. 1994, pp. 401-424.
Kuehlmann, A., “Equivalence Checking Using Cuts and Heaps,” IBM Thomas J. Watson Research Center, Yorktown Heights, NY U.S.A., 1997, pp. 263-268.
Pawlovsky, et al., “Verification of Register Transfer Level (RTL) Designs,” IEEE International Conference, 1989, pp. 91-94.
Stoffel, D. et al., “Logic Equivalence Checking by Optimization Techniques,” Proc. Int'l. Workshop on CAD, Test and Evaluation for Dependability, Jul. 1996, pp. 85-90.
Vakilotojar, et al., “RTL Verification of Timed Asynchronous and Heterogeneous Systems Using Symbolic Model Checking,” IEEE Design Automation Conference, 1997, pp. 181-188.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Similarity-driven synthesis for equivalence checking of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Similarity-driven synthesis for equivalence checking of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Similarity-driven synthesis for equivalence checking of... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3665443

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.