Silicon wafers and method of fabricating the same

Details Silicon wafers and method of fabricating the same Silicon wafers and method of fabricating the same

2007-06-20

2010-06-08

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Radiation or energy treatment modifying properties of...

C117S002000, C117S003000

Reexamination Certificate

active

07732352

ABSTRACT:
By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the disclosed two-step rapid thermal process, the distribution of defects can be accurately controlled and an ideal device active zone can be formed up to a certain distance from the surfaces of the wafer. In addition, it is possible to maximize the internal gettering (IG) efficiency by enabling the oxygen precipitates and the bulk stacking faults to have constant densities in the depth direction in an internal region of the wafer, that is, the bulk region. In order to obtain the constant concentration profile of the oxygen precipitates and the bulk stacking faults in the bulk region, the wafer is subjected to the aforementioned two-step rapid thermal process in a predetermined mixed gas atmosphere.

REFERENCES:
patent: 4868133 (1989-09-01), Huber
patent: 5401669 (1995-03-01), Falster et al.
patent: 5403406 (1995-04-01), Falster et al.
patent: 5502010 (1996-03-01), Nadahara et al.
patent: 5502331 (1996-03-01), Inoue et al.
patent: 5994761 (1999-11-01), Falster et al.
patent: 6139625 (2000-10-01), Tamatsuka et al.
patent: 6245311 (2001-06-01), Kobayashi et al.
patent: 6336968 (2002-01-01), Falster
patent: 6339016 (2002-01-01), Torack et al.
patent: 6413310 (2002-07-01), Tamatsuka et al.
patent: 6485807 (2002-11-01), Park
patent: 6503594 (2003-01-01), Park
patent: 6573159 (2003-06-01), Kobayashi et al.
patent: 6641888 (2003-11-01), Asayama et al.
patent: 6642123 (2003-11-01), Mun et al.
patent: 6663708 (2003-12-01), Morita et al.
patent: 6680260 (2004-01-01), Akiyama et al.
patent: 6803331 (2004-10-01), Holzl et al.
patent: 7011717 (2006-03-01), Kobayashi et al.
patent: 7078357 (2006-07-01), Tobe et al.
patent: 7081422 (2006-07-01), Hayamizu et al.
patent: 7135351 (2006-11-01), Binns et al.
patent: 7242075 (2007-07-01), Mun et al.
patent: 7442253 (2008-10-01), Falster et al.
patent: 7485928 (2009-02-01), Falster et al.
patent: 2002/0100410 (2002-08-01), Kim et al.
patent: 2003/0013321 (2003-01-01), Hayamizu et al.
patent: 2005/0054124 (2005-03-01), Mun et al.
patent: 2005/0247259 (2005-11-01), Yoon et al.
patent: 1256723 (2000-06-01), None
patent: 10-2002-0052562 (2002-07-01), None
patent: 2002-0052565 (2002-07-01), None
patent: 10-2003-0002300 (2003-01-01), None
patent: 2003-0002300 (2003-01-01), None
patent: WO 98-45507 (1998-10-01), None
patent: WO 98/45507 (1998-10-01), None
patent: WO 98/45508 (1998-10-01), None
patent: WO 98/45509 (1998-10-01), None
patent: WO 2004/070824 (2004-08-01), None
Office Action issued by Korean Intellectual Property Office (dated May 27, 2005) for counterpart priority application KR 10-2003-062283.
Office Action from the Chinese Patent Office for Chinese Application No. 200410005410.1, corresponding to U.S. Appl. No. 10/699,438.
English translation of the office action for Chinese Application No. 200410005410.1.

Affiliated with

Also associated with

Rating

Silicon wafers and method of fabricating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Silicon wafers and method of fabricating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon wafers and method of fabricating the same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4175965