Silicon tab edge mount for a wafer level package

Details Silicon tab edge mount for a wafer level package Silicon tab edge mount for a wafer level package

2011-04-26

2011-04-26

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Physical deformation

C257S678000, C257S691000, C257S692000, C257S693000, C257S787000

Reexamination Certificate

active

07932570

ABSTRACT:
A Micro-ElectroMechanical Systems (MEMS) device having electrical connections (a metallization pattern) available at an edge of the MEMS die. The metallization pattern on the edge of the die allows the die to be mounted on edge with no further packaging, if desired.

REFERENCES:
patent: 2008/0315390 (2008-12-01), Kuhmann et al.
patent: 2009/0152653 (2009-06-01), Borzabadi et al.

Affiliated with

Also associated with

Rating

Silicon tab edge mount for a wafer level package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Silicon tab edge mount for a wafer level package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon tab edge mount for a wafer level package will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2730167