Silicon substrate for package

Details Silicon substrate for package Silicon substrate for package

2011-08-02

2011-08-02

Nguyen, Dao H (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With electrical contact in hole in semiconductor

Reexamination Certificate

active

07989927

ABSTRACT:
In a silicon substrate for a package, a through electrode is provided with which a through hole passing through from a bottom surface of a cavity for accommodating a chip of an electronic device to a back surface of the substrate is filled. An end part of the through electrode in the bottom surface side of the cavity has a connection part to a wiring that forms an electric circuit including the chip of the electronic device. The silicon substrate for a package is characterized in that (1) a thin film wiring is included as the wiring and the connection part is reinforced by a conductor connected to the thin film wiring and/or (2) a wire bonding part is included as the wiring and the connection part is formed by wire bonding the end part of the through electrode in the bottom surface side of the cavity.

REFERENCES:
patent: 6888209 (2005-05-01), Jobetto
patent: 7081665 (2006-07-01), Wood et al.
patent: 7750358 (2010-07-01), Shiraishi et al.
patent: 2007/0018190 (2007-01-01), Kim et al.
patent: 2008/0136022 (2008-06-01), Filoteo et al.
patent: 2008/0136038 (2008-06-01), Savastiouk et al.
patent: 2007-208041 (2007-08-01), None

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