Active solid-state devices (e.g. – transistors – solid-state diode – With specified dopant – Deep level dopant
Reexamination Certificate
2000-03-10
2003-04-15
Picardat, Kevin M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
With specified dopant
Deep level dopant
C117S013000, C117S019000
Reexamination Certificate
active
06548886
ABSTRACT:
TECHNICAL FIELD
This invention relates to improvements in and concerning the quality of a silicon semiconductor substrate, more particularly to a silicon semiconductor substrate which allows exclusion of a defect from the interior or surface of the substrate and permits formation of devices on the substrate in an exalted yield, and a method for the production thereof.
This invention relates further to improvements in and concerning the quality of an epitaxial silicon semiconductor substrate, more particularly to an epitaxial semiconductor substrate which, owing to the exclusion of a defect from the epitaxial layer and from the neighborhood of the interface between the epitaxial layer and a substrate wafer and the improvement in gettering ability, permits formation of devices on the epitaxial substrate in an exalted yield, and a method for the production thereof.
RELATED ART
It is known that in consequence of the improvement attained in recent years in the degree of integration of devices, minute defects existing on the surface and near the surface layer of a silicon semiconductor substrate since immediately after manufacture of the substrate and crystal defects induced during the course of production of devices result in lowering the yield of production of devices as by inducing impairment of device patterns during the formation of devices and imperfecting the devices in performance. As the cause for this lowered yield of devices, the defects called “crystal originated particles” or “crystal originated pits” (COP) that are detected in the form of pits, about 0.1 &mgr;m in size, on the surface of a substrate immediately after manufacture of the substrate have been attracting attention.
The reason for calling the defects by this name is that when a silicon semiconductor substrate is etched with an ammonia-hydrogen peroxide liquid mixture, pits which originate in lattice defects in a crystal manifest themselves on the surface of the substrate and these pits are detected during the determination with a testing device adapted to take count of particles on the substrate surface. The COP is a term for designating all the defects that are detected by such method of determination. In the single silicon crystal which is grown by the ordinary Czochralski (CZ) method or the CZ method using an applied magnetic field, these defects are considered to be actually octahedral voids (hereinafter referred to as “void defects”) in the crystal. It is inferred that these void defects induce the devices to suffer from impairment of patterns or compel the devices to incur structural breakage. To date, several techniques have been proposed with a view to decreasing or disappearing the COP which is harmful to the manufacture of devices.
As a technique for disappearing the COP, the method which consists in limiting the speed of growth of a single crystal to not more than 0.8 mm/min (JP-A-02-267,195) has been known. This method is intended to repress the occurrence of supersaturated vacancy-type point defects (vacancies) in a single crystal being grown during the course of cooling by decreasing the amount of vacancies, i.e. an element which gives rise to void defects, to be introduced into the interface of growth of the crystal and slackening the speed of cooling the crystal as well. This method, however, entails such problems as deriving a decrease in productivity from a fall in the speed of growth and, at the same time, generating such crystal defects as dislocation loops which are different in kind from the COP.
As techniques for repressing the generation of COP, the method of controlling the behavior of a single crystal in the course of cooling and particularly the method of controlling the time required by the single crystal in passing an approximate range of temperature from 1200° C. to 1000° C. have been known to be effective (JP-A-08-12,493, JP-A-08-91,983, and JP-A-09-227,289). These techniques pose no problem in terms of productivity because they bring no noticeable decrease in the speed of growth of the single crystal. Since they have the lower limits of decrease of the density of COP generally in the neighborhood of 10
5
pieces/cm
3
, they encounter difficulty in attaining a further decrease in the density to not more than 10
4
pieces/cm
3
, for example.
As a technique for decreasing the COP, the method which comprises limiting the time for retaining a single crystal, while the crystal is in the process of being cooled during the growth thereof, in a temperature range of 850° C.-1100° C. to less than 80 minutes or attaining in the growth of a crystal a silicon single crystal having a nitrogen concentration of 1×10
14
/cm
3
and thereafter manufacturing the silicon single crystal into a silicon wafer and heat-treating the wafer at a temperature of not less than 1000° C. for not less than one hour (JP-A-10-98,047). This technique is intended to abolish defects during the heat treatment by shifting the size distribution of the COP generated during the production of the crystal toward the smaller side. Since it is generally held that the effect of this decrease in size gains in prominence in accordance as the oxygen concentration decreases, however, this technique is not put to use at the oxygen concentration of 7×10
17
-10×10
17
/cm
3
which is commonly used in the Czochralski method. Thus, it is difficult to establish compatibility between the impartation of the gettering ability which utilizes the formation of an oxygen precipitate in the substrate generally attained by increasing the oxygen concentration in the substrate and the decrease of the COP.
In addition to the technique for decreasing the COP during the growth of a single crystal, the technique which effects decrease or disappearance of the COP on the surface of a substrate by slicing and polishing a single crystal and manufacturing it into a substrate and thereafter subjecting the substrate to a heat treatment has been known. JP-A-03-233,936, for example, proposes the performance of a heat treatment at 800-1250° C. for not more than 10 hours. When the heat treatment is carried out in an oxidizing atmosphere indicated in a working example which is cited in this patent publication, however, it is at a disadvantage in inducing an increase in the number of pits formed on the surface of the substrate because the etching by oxidation of the surface of the substrate entails etch pits of void defects to the surface of the substrate and, at the same time, rendering it difficult to lower the density of COP within a depth of 1 &mgr;m from the surface of the substrate below 10
4
pieces/cm
3
. Then, JP-A-59-202,640 proposes the performance of a heat treatment in an atmosphere of hydrogen. Though this method, owing to the use of the atmosphere of hydrogen, is capable of abolishing the COP on the outermost surface and lowering the COP density within a depth of 0.5 &mgr;m from the surface below 10
4
pieces/cm
3
, it is incapable of lowering the density of the COP in a deeper portion from the surface below 10
4
pieces/cm
3
and unsatisfactory for the formation of a defectless layer from the viewpoint of the manufacture of devices. Moreover, this method uses an explosive atmosphere of hydrogen and, therefore, requires a perfect measure for safety.
Concerning the doping of nitrogen preparatory to the growth of a single crystal of silicon, methods for the doping have been known as from JP-A-60-251,190, etc. In search of the effect of doping of nitrogen on the floating zone (FZ) single crystal, JP-A-57-17,497 discloses a method for enhancing the strength of crystal and JP-A-08-91,993 a method for repressing variation in the resistance. Then, JP-A-05-294,780 has a disclosure to the effect that the nitrogen doped into silicon acts on or binds with vacancies, i.e. one form of complexes, and consequently represses the formation of vacancy participated clusters (void defects) and curbs the occurrence of etch pits which are thought to originate in void defects. It has been reported by D. Graf et al. (The Electrochemical Society Proceedin
Hasebe Masami
Hoshino Taizo
Ikari Atsushi
Iwasaki Toshio
Nakai Katsuhiko
Picardat Kevin M.
Wacker NSCE Corporation
Wenderoth , Lind & Ponack, L.L.P.
LandOfFree
Silicon semiconductor wafer and method for producing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Silicon semiconductor wafer and method for producing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon semiconductor wafer and method for producing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3013130