Silicon semiconductor devices with &dgr;-doped layers

Details Silicon semiconductor devices with &dgr;-doped layers Silicon semiconductor devices with &dgr;-doped layers

1999-10-29

2002-06-11

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S510000, C438S511000, C438S512000, C438S516000

Reexamination Certificate

active

06403454

ABSTRACT:

FILED OF THE INVENTION
This invention relates generally to silicon (Si) semiconductor devices having &dgr;-doped layers and, more particularly, to integrated circuits incorporating such devices.
BACKGROUND OF THE INVENTION
In semiconductor devices grown by techniques that allow for a high degree of control of layer thickness and dopant concentration (e.g., molecular beam epitaxy or MBE) it is known to form extremely thin layers that have very high levels of dopant concentration (e.g., concentrations in excess of 10
20
cm
−3
). Thin highly doped layers of this type are known as delta-doped or &dgr;-doped layers. Their thickness is so small, relative to a characteristic length of the material (e.g., a Debye length), that these layers are also referred to as two-dimensional (2D) layers, as contrasted with much thicker layers that are known as three-dimensional (3D) layers.
The dopant concentration and the free-carrier concentration (or density), however, are typically not the same. As the dopant concentration increases, it is well known that the free-carrier concentration will eventually saturate. This behavior in Si has been attributed to the formation of electrically inactive precipitates and/or deactivating dopant centers containing vacancies. Recently, a new class of deactivating defects in Si without vacancies, called donor pairs (DP), has been proposed to explain the observed electrical saturation. See, D. J. Chadi et al.,
Phys. Rev. Lett
., Vol. 79, No. 24, p. 4834 (1997), which is co-authored by two of us (P. H. Citrin and H-J. Gossmann) and is incorporated herein by reference. Formation of DP defects depends only on dopant concentration rather than on sample preparation conditions, so even if preparation is adjusted to avoid precipitates or vacancy-containing centers, electrical saturation will still occur. Chadi et al. at page 4837, col. 1, reported that the free-carrier concentration saturated at a maximum of about 6.5×10
20
cm
−3
and concluded that DP defects represent an inherent limitation to electron activity of Si doped with group V donors.
Such a barrier to achieving full electrical activity in highly doped Si should be particularly severe for 2D &dgr;-doped layers, where even higher dopant densities can, in principle, be obtained. See, S. J. Bass,
J. Cryst. Growth
, Vol. 47, p.613 (1979), which is incorporated herein by reference. Free-carrier areal concentrations (n
e
) of up to about 3×10
14
cm
−2
have been reported in 2D layers (See, H.-J. Gossmann et al.,
Phys. Rev
., Vol. 47, No. 19, p. 12618 (1993), which is incorporated herein by reference.), but because the &dgr;-doped layer thicknesses in those samples were not determined, the effective volume concentration of dopants was not known. Conversely, samples from which reliably measured &dgr;-doped layer thicknesses were reported had no corresponding measurements of electrical activity. See, W. F. J. Slijkerman et al.,
J. Appl. Phys
., Vol. 68, No. 10, p. 5105 (1990) and A. R. Powell et al.,
J. Cryst. Growth
, Vol. 111, p. 907 (1991), which are incorporated herein by reference. Consequently, the importance of DP defects in 2D &dgr;-doped Si layers, and thus the inherent limitations on free-carrier densities, in general, has heretofore not been possible to assess accurately.
SUMMARY OF THE INVENTION
We have discovered that, contrary to conventional wisdom about forming DP defects, electrical saturation in highly doped 2D layers of Si does not occur. In accordance with one aspect of our invention, free-carrier concentrations in excess of about 7×10
20
cm
−3
can be attained in single crystal Si layers &dgr;-doped with a Group V element. In one embodiment, free-carrier concentrations in excess of about 2×10
21
cm
−3
are realized in single crystal Si that is &dgr;-doped with Sb. In another embodiment, the &dgr;-doped layer is an integral part of an FET; e.g., it may be located under the spacers, near the top of the source drain regions, and/or near the top of the gate stack. In accordance with another aspect of our invention, an integrated circuit is fabricated by the steps of providing a single crystal silicon body and forming a doped layer in the body, characterized in that the processing steps form neither a significant amount of electrically inactive precipitates nor a significant number of deactivating dopant centers containing vacancies, and the layer is fabricated as a &dgr;-doped layer that is doped with a Group V element, so that the free-carrier density in the layer is in excess of about 7×10
20
cm
−3
, preferably in excess of about 2×10
21
cm
−3
.


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Gossmann et al., Dopant electrical activity and majority-carrier mobility in B-and Sb-&dgr;-doped Si thin films, Phys. Rev. B, vol. 47, No. 19, pp. 12618-12624 (May 1993).
Slijkerman et al., X-ray reflectivity of an Sb-delta-doping layer in silicon, J. Appl. Phys., vol. 68, No. 10, pp. 5105-5108 (Nov. 1990).
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