Silicon packages for power semiconductor devices

Electricity: electrical systems and devices – Safety and protection of systems and devices – With specific current responsive fault sensor

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357 38, 357 67, 357 72, 357 79, 357 81, 361386, H01L 2306

Patent

active

047454555

ABSTRACT:
A hermetically sealed package for a power semiconductor wafer is provided comprising substantially entirely silicon materials selected to have coefficients of thermal expansion closely matching that of the power semiconductor wafer. A semiconductor wafer such as a power diode comprises a layer of silicon material having first and second device regions on respective sides thereof. An electrically conductive cap and base, each including a layer of silicon material, are disposed in electrical contact with the first and second regions of the semiconductor device, respectively. An electrically insulative sidewall of silicon material surrounds the semiconductor wafer, is spaced from an edge thereof, and is bonded to the cap and base for hermetically sealing the package. An electrical passivant is disposed on an edge of the semiconductor wafer adjoining the first and second device regions for preventing electrical breakdown between the cap and base. An arc suppressant is disposed within the package between the semiconductor wafer edge and the sidewall for preventing electrical arcing between the base and cap.

REFERENCES:
patent: 3354258 (1967-11-01), Saia et al.
patent: 3643136 (1972-02-01), Tuft
patent: 3688018 (1972-08-01), Hiscocks
patent: 3721867 (1973-03-01), Schierz
patent: 3925808 (1975-12-01), Rai-Choudbury
patent: 3986201 (1976-10-01), Herold et al.
patent: 3996602 (1976-12-01), Goldberg et al.

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