Silicon oxide co-deposition/etching process

Details Silicon oxide co-deposition/etching process Silicon oxide co-deposition/etching process

1999-02-25

2001-05-01

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S689000, C438S694000, C438S695000, C438S758000, C438S787000

Reexamination Certificate

active

06225228

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of semiconductor manufacturing. More particularly, the present invention provides methods of simultaneously depositing and etching silicon oxide on a substrate.
BACKGROUND OF THE INVENTION
Silicon oxide is a useful isolation material used in many semiconductor processes. In one use, silicon oxide can be used as a spacer to provide sloped sidewalls on semiconductor structures with generally vertical sidewalls, such as transistors, trace lines, etc. Because the silicon oxide material has a low dielectric constant, it can also be used to electrically isolate the structures.
Known processes of providing silicon oxide spacers involve a first step of depositing doped or undoped silicon oxide on the semiconductor structures. The silicon oxide can be deposited by a variety of methods including chemical vapor deposition (CVD) and plasma-enhanced chemical vapor deposition (PECVD). Source gases for the silicon oxide layers include silane and tetraethyl orthosilicate (TEOS). Silicon oxide deposited employing PECVD with a TEOS source gas is particularly useful in some instances because the processing temperatures needed for deposition are lower than standard chemical vapor deposition temperatures, i.e., typically about 375° C. Another advantage of PECVD with a TEOS source gas is that it can be used to deposit silicon oxide in between adjacent sidewalls having larger aspect ratios than PECVD or CVD methods using silane as a source gas.
After the layer of silicon oxide is deposited, sloped sidewalls are provided by etching the silicon oxide and/or by reflowing the silicon oxide layer at high temperatures (where those temperatures will not adversely affect any other layers or structures already on the semiconductor wafer). These additional steps of etching and/or reflowing the silicon oxide are performed separately from the step of depositing the silicon oxide, i.e., after the silicon oxide layer has been deposited. As a result, additional time is required for processing—thereby increasing the cost of manufacturing the semiconductor devices on the wafer. In addition, in many instances, the temperatures needed for reflow are not safe to use with the semiconductor wafer.
One particular application in which silicon oxide is used is in the manufacture of stacked capacitor DRAM cells.
FIG. 1
is an idealized representation of a stacked capacitor DRAM cell depicting the transistor with a layer of silicon oxide
10
deposited on the top surface
16
and sidewalls
12
in the transistor. This view is idealized in that the actual DRAM cell will not usually have orthogonal features. The initial deposition step in which the silicon oxide
10
is deposited results in a generally uniform layer of oxide over the sidewalls
12
, the bottom surface
14
between the sidewalls, and the top surfaces
16
over the electrodes in the transistor. The silicon oxide layer
10
can then be etched using any suitable method to form facets
18
(see
FIG. 2
) proximate the intersection between the sidewalls
12
and top surfaces
16
.
Typically, a number of layers of silicon oxide
10
are deposited and etched until the desired facets
18
are obtained. As a result, the wafer may be subjected to a number of discrete, sequential deposition and etching process steps to obtain the desired faceted or sloped sidewalls needed to ensure complete coverage of the bottom surfaces
14
between sidewalls
12
by both the silicon oxide and later-deposited layers. Those multiple deposition and etching steps add to the cost of the wafers and reduce throughput of the process.
SUMMARY OF THE INVENTION
The present invention provides methods of providing silicon oxide on a substrate in a single process step as opposed to multiple sequential deposition-etch-deposition methods. In addition, if the etch gas contains fluorine, the resulting silicon oxide will also contain fluorine, thereby reducing its dielectric constant which further enhances the insulating properties of the silicon oxide.
The method involves simultaneously introducing both a source gas and an etch gas into a CVD chamber. As a result, the method will typically involve simultaneous deposition and etching of the silicon oxide.
In one aspect according to the present invention, the method includes the steps of depositing silicon oxide on a substrate by contacting the substrate with a plasma enhanced source gas, and contacting the silicon oxide with a plasma enhanced etching gas at the same time as the silicon oxide is deposited.
In another aspect according to the present invention, the method includes forming a silicon oxide spacer on a substrate by depositing silicon oxide on the substrate by contacting the substrate with a plasma enhanced source gas, and contacting the silicon oxide with a plasma enhanced etching gas at the same time as the silicon oxide is deposited.
In another aspect according to the present invention, the method includes forming a silicon oxide spacer on a substrate by providing a substrate in a chamber; providing a plasma enhanced source gas in the chamber, wherein silicon oxide is formed on the substrate; and providing a plasma enhanced etching gas in the chamber at the same time as the source gas is provided in the chamber; wherein a silicon oxide spacer is formed on the substrate.
In another aspect according to the present invention, the method includes depositing a silicon oxide spacer on a DRAM cell by contacting the cell with a plasma enhanced source gas, wherein silicon oxide is formed on the cell, and contacting the silicon oxide with a plasma enhanced etching gas at the same time as he silicon oxide is deposited.
In another aspect according to the present invention, the method includes forming a silicon oxide spacer on a DRAM cell by depositing silicon oxide on the cell by contacting the cell with a plasma enhanced source gas, and contacting the silicon oxide with a plasma enhanced etching gas at the same time as the silicon oxide is deposited.
In another aspect according to the present invention, the method includes forming a silicon oxide spacer on a DRAM cell by providing a DRAM cell in a chamber; providing a plasma enhanced source gas in the chamber, wherein silicon oxide is formed on the DRAM cell; and providing a plasma enhanced etching gas in the chamber at the same time as the source gas is provided in the chamber; wherein a silicon oxide spacer is formed on the DRAM cell.
These and other features and advantages of methods according to the present invention will become more apparent upon reviewing the detailed description of the invention below.


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