Silicon on silicon package with precision align macro

Details Silicon on silicon package with precision align macro Silicon on silicon package with precision align macro

1999-04-12

2000-12-26

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

257665, 257779, 257685, H01L 2334, H01L 2348, H01L 2352

Patent

active

061664375

ABSTRACT:
A silicon wafer is etched to form a first and second series of guidance features. The features of the first series are larger than and surround the features of the second series. The second series is clustered into groups and a hole is formed in the center of each group. The wafer is designed to integrate a silicon package having preformed contacts with a plurality of silicon-based chips. The package and each chip has a series of guidance recesses which correspond to the guidance features of the first and second series, respectively. One chip is placed on top of each group of the second series, and the package is placed on top of the first series. The recesses in the package and chips will precisely align with and slidingly engage the upper ends of the features. Since the features of the first series are larger than those of the second series, there is a clearance between the package and the chips. In the final stage of assembly, the package is restrained from movement and a pin is inserted through each hole in the wafer to force the chips into contact with the contacts on the package. Heat is then applied to fuse solder balls on the chips with the contacts to form a complete and finished assembly.

REFERENCES:
patent: 5814885 (1998-09-01), Pogge et al.
patent: 6020624 (2000-02-01), Wodd et al.
patent: 6042391 (2000-03-01), Bodo et al.

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