Silicon-on-insulator vertical array device trench capacitor...

Details Silicon-on-insulator vertical array device trench capacitor... Silicon-on-insulator vertical array device trench capacitor...

1999-10-25

2003-05-20

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S388000, C438S392000

Reexamination Certificate

active

06566177

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memories and, more particularly, to a trench capacitor dynamic random access memory cell with a vertical silicon on insulator access transistor for semiconductor memories.
2. Background Description
Dynamic Random Access Memory (DRAM) cells are well known. A DRAM cell is essentially a capacitor for storing charge and a pass transistor (also called a pass gate or access transistor) for transferring charge to and from the capacitor. Data (1 bit) stored in the cell is determined by the absence or presence of charge on the storage capacitor. Because cell size determines chip density, size and cost, reducing cell area is one of the DRAM designer's primary goals. Reducing cell area is done, normally, by reducing feature size to shrink the cell.
Besides shrinking the cell features, the most effective way to reduce cell area is to reduce the largest feature in the cell, typically, the area of the storage capacitor. Unfortunately, shrinking the capacitor plate area reduces capacitance and, consequently, reduces stored charge. Reduced charge means that what charge is stored in the DRAM is more susceptible to noise, soft errors, leakage and other well known DRAM problems. Consequently, another primary goal for DRAM cell designers is to maintain storage capacitance while reducing cell area.
One way to accomplish this density goal without sacrificing storage capacitance is to use trench capacitors in the cells. Typically, trench capacitors are formed by etching long deep trenches in a silicon wafer and, then, placing each capacitor on its side in the trench, orienting the capacitors vertically with respect to the chip's surface. Thus, the surface area required for the storage capacitor is dramatically reduced without sacrificing capacitance, and correspondingly, storable charge.
However, since using a trench capacitor eliminates much of the cell surface area, i.e., that portion of cell area which was formerly required for the storage capacitor, the cell's access transistor has become the dominant cell feature determining array area. As a result, to further reduce cell and array area, efforts have been made to reduce access transistor area, which include making a vertical access transistor in the capacitor trench. See, for example, U.S. Pat. No. 5,006,909 entitled “DRAM With A Vertical Capacitor And Transistor” to Kosa.
Other approaches to using a vertical access transistor include U.S. Pat. No. 4,673,962 entitled “Vertical DRAM Cell and Method” to Chatterjee et al. and U.S. Pat. No. 5,102,817 entitled “Vertical DRAM Cell and Method” to Chatterjee et al. which both teach a vertical DRAM cell with a polysilicon channel access transistor. The polysilicon channel access transistor is formed in the same vertical polysilicon layer that serves as the cell storage capacitor plate.
U.S. Pat. No. 5,164,917 entitled “Vertical One-transistor DRAM With Enhanced Capacitance And Process for Fabricating” to Shichijo, U.S. Pat. No. 5,208,657 entitled “DRAM Cell With Trench Capacitor And Vertical Channel in Substrate” to Chatterjee et al., U.S. Pat. No. 5,225,697 entitled “Vertical DRAM Cell and Method” to Malhi et al. and U.S. Pat. No. 5,252,845 entitled “Trench DRAM Cell With Vertical Transistor” to Kim et al. all teach memory cells formed in small square deep trenches that have vertical access transistors. Further, the access transistor is annular, essentially, and formed on the trench sidewalls above the cell trench capacitor. Both Kim et al. and Shichijo teach DRAM cells wherein a layered storage capacitor is formed in and entirely enclosed in the trench.
For another approach, U.S. Pat. No. 5,103,276 entitled “High Performance Composed Pillar DRAM Cell” to Shen et al., U.S. Pat. No. 5,300,450 entitled “High Performance Composed Pillar DRAM Cell” to Shen et al. and U.S. Pat. No. 5,334,548 entitled “High Performance Composed Pillar DRAM Cell” to Shen et al. teach etching a grid-like pattern to form individual pillars. A common capacitor plate is formed at the bottom of the pillars. A diffusion on all sides of the bottom of the cell pillar serves as a cell storage node. Each pillar's storage diffusion is isolated from adjacent pillars by a dielectric pocket formed beneath the common capacitor plate. An access transistor channel is along one side of each pillar and disposed between the storage node and a bitline diffusion, which is at the top of the pillar. The access transistor gate is formed on one side of the pillar, above the common capacitor plate.
U.S. Pat. No. 5,281,837 entitled “Semiconductor Memory Device Having Cross-Point DRAM Cell Structure” to Kohyama, U.S. Pat. No. 5,362,665 entitled “Method of Making Vertical DRAM Cross-Point Memory Cell” to Lu and U.S. Pat. No. 5,710,056 entitled “DRAM With a Vertical Channel Structure And Process For Manufacturing The Same” to Hsu teach yet another approach wherein DRAM cells have their storage capacitor formed above the access transistor. U.S. Pat. No. 5,504,357 entitled “Dynamic Random Access Memory having A Vertical Transistor” to Kim et al. teaches a buried bitline transistor with the bitline formed at the bottom of a trench and the storage capacitor is formed above the transistor, at the wafer surface.
Performance is equally as important as density to DRAM design. Silicon-on-insulator (SOI) has be used to decrease parasitic capacitance and hence to improve integrated circuit chip performance. SOI reduces parasitic capacitance within the integrated circuit to reduce individual circuit loads, thereby improving circuit and chip performance. However, reducing parasitic capacitance is at odds with increasing or maintaining cell storage capacitance. Accordingly, SOI is seldom used for DRAM manufacture. One attempt at using SOI for DRAMS is taught in U.S. Pat. No. 5,888,864 entitled “Manufacturing Method of DRAM Cell Formed on An Insulating Layer Having a Vertical Channel” to Koh et al. Koh et al. teaches a SOI DRAM formed in a dual sided wafer circuit fabrication process. In the dual sided wafer fabrication process of Koh et al. storage capacitors are formed on one side of the wafer and, the access transistors are formed on the other side of the wafer.
Thus, there is a need for increasing the number of stored data bits per chip of Dynamic Random Access Memory (DRAM) products. There is also a need for improving DRAM electrical performance without impairing cell charge storage.
SUMMARY OF THE INVENTION
It is therefore a purpose of the present invention to increase the Dynamic Random Access Memory (DRAM) integration packing density;
It is another purpose of the present invention to decrease DRAM cell area;
It is yet another purpose of the present invention to increase the number of bits per DRAM chip;
It is yet another purpose of the present invention to reduce parasitic capacitance within DRAM chips;
It is yet another purpose of the present invention to improve DRAM electrical performance;
It is yet another purpose of the invention to achieve trench capacitor DRAM cell density while benefitting from the reduced parasitic capacitance, leakage and improved performance of silicon on insulator technology.
The present invention is a vertical trench-capacitor Dynamic Random Access Memory (DRAM) cell and array in a Silicon-On-Insulator (SOI) substrate and an SOI DRAM chip. The cell has a vertical trench capacitor and an insulated gate Field Effect Transistor (FET) formed on the trench sidewall. A buried oxide layer (BOX) in the SOI substrate forms a protective sidewall collar along the upper edge of the capacitor region. The vertical FET is formed along the upper sidewall of the trench, above the trench capacitor. A polysilicon strap formed along the sidewall at the BOX layer forms a self-aligned contact between the trench capacitor and the vertical FET. Thus, the cell occupies less horizontal chip area than a conventional planar DRAM cell.
The cells are formed in a silicon wafer by first forming the buried oxide layer in the wafer. Deep

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