Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-04-30
2002-11-12
Ho, Hoai (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000, C257S347000, C257S386000, C257S408000, C438S149000, C438S151000, C438S682000
Reexamination Certificate
active
06479868
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to silicon-on-insulator (SOI) devices and methods of forming the same and, more particularly, to SOI devices and methods for forming which avoid or reduce floating body effects and reduce junction capacitance.
BACKGROUND ART
Silicon-on-insulator (SOI) materials offer potential advantages over bulk materials for the fabrication of high performance integrated circuits. Dielectric isolation and reduction of parasitic capacitance improve circuit performance, and virtually eliminate latch-up in CMOS circuits. In addition, circuit layout in SOI can be greatly simplified and packing density greatly increased if the devices are made without body contacts (i.e., if the body regions of these devices are “floating”). However, partially-depleted metal oxide semiconductor field effect transistors (MOSFETs) on SOI materials typically exhibit parasitic effects due to the presence of the floating body (“floating body effects”). These floating body effects may result in undesirable performance in SOI devices.
It will be appreciated from the foregoing that a need exists for SOI MOSFETs having reduced floating body effects.
In addition, reducing junction capacitance in SOI devices is also desirable to, in part, increase the switching speed of the device.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is a silicon-on-insulator (SOI) transistor. The SOI transistor includes a germanium implanted source and drain having a body disposed therebetween, and a gate disposed on the body, the germanium being implanted at an angle such that the source has a concentration of germanium at a source/body junction and the gate shields germanium implantation in the drain adjacent a drain/body junction resulting in a graduated drain/body junction.
According to another aspect of the invention, the invention is a method of fabricating a silicon-on-insulator (SOI) transistor. The method includes the steps of providing an active layer disposed on a buried oxide (BOX) layer, the BOX layer being disposed on a substrate, the active layer having an active region defined by isolation regions; forming a transistor in the active region, the transistor having a source and a drain having a body disposed therebetween, and a gate disposed on the body; and implanting the transistor with germanium, the germanium implanted at an angle such that a concentration of germanium is present at a source/body junction and the gate shields germanium implantation in the drain adjacent a drain/body junction resulting in a graduated drain/body junction.
According to another aspect of the invention, the invention is a silicon-on-insulator (SOI) transistor. The SOI transistor includes a source and drain having a body disposed therebetween, and a gate disposed on the body, the source and drain implanted with atoms selected from silicon, argon, krypton and xenon, the atoms being implanted at an angle such that the source has a concentration of atoms at a source/body junction and the gate shields atom implantation in the drain adjacent a drain/body junction resulting in a graduated drain/body junction.
REFERENCES:
patent: 5578865 (1996-11-01), Vu et al.
patent: 5686735 (1997-11-01), Sim
patent: 6054386 (2000-04-01), Prabhakar
patent: 6198142 (2001-03-01), Chau et al.
patent: 6339005 (2002-01-01), Bryant et al.
An Xilin Judy
Riccobene Concetta E.
Yu Bin
Advanced Micro Devices , Inc.
Ho Hoai
Renner , Otto, Boisselle & Sklar, LLP
Tran Mai-Huong
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