Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-26
2002-07-02
Ho, Hoai V. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S324000
Reexamination Certificate
active
06414355
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to silicon-on-insulator (SOI) integrated circuits having analog devices and digital devices on one substrate and, more particularly, to an SOI chip having an active layer of non-uniform thickness to allow the fabrication of partially depleted transistors for digital circuitry and fully depleted transistors for analog circuitry.
BACKGROUND ART
Traditional silicon-on-insulator (SOI) integrated circuits typically have a silicon substrate having a buried oxide (BOX) layer disposed thereon. An active layer (also referred to as a silicon layer) is disposed on the BOX layer. Within the active layer, active devices, such as a transistors, are formed in active regions. The size and placement of the active regions are defined by shallow trench isolation (STI) regions. Therefore, the active devices are isolated from the substrate by the BOX layer. As is well known in the art, the foregoing traditional SOI structure provides significant advantages when constructing transistors for digital circuitry. More specifically, transistors constructed in SOI format have floating body effects which lead to the devices being partially depleted during operation.
However, in some instances, it may be desirable to fabricate analog circuitry on a chip also having SOI-based digital circuitry. Generally, analog circuitry performs better when made from fully depleted devices having less floating body effects than the devices used for the digital circuitry.
Accordingly, there exists a need in the art for hybrid, or mixed digital signal and analog signal, SOI chips with regions respectively suited for digital circuitry and analog circuitry.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is a silicon-on-insulator (SOI) chip. The SOI chip has a substrate; a buried oxide (BOX) layer disposed on the substrate; and an active layer disposed on the BOX layer, the active layer divided into a first and a second tile, the first tile having a first thickness and the second tile having a second thickness, the second thickness being smaller than the first thickness.
According to another aspect of the invention, the invention is a method of fabricating a silicon-on-insulator (SOI) chip having an active layer with a non-uniform thickness. The method includes the steps of providing a substrate; providing a buried oxide layer (BOX) on the substrate; providing an active layer on the BOX layer, the active layer having an initially uniform thickness; dividing the active layer into at least a first and a second tile; and altering the thickness of the active layer in the area of the second tile.
REFERENCES:
patent: 5973358 (1999-10-01), Kishi
patent: 5973364 (1999-10-01), Kawanaka
patent: 6314021 (2001-11-01), Maeda et al.
An Judy Xilin
En William G.
Yu Bin
Advanced Micro Devices , Inc.
Ho Hoai V.
Renner , Otto, Boisselle & Sklar, LLP
Tran Long K.
LandOfFree
Silicon-on-insulator (SOI) chip having an active layer of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Silicon-on-insulator (SOI) chip having an active layer of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon-on-insulator (SOI) chip having an active layer of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2832968