Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-07
2002-04-30
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S290000, C257S350000, C348S302000, C348S308000, 43
Reexamination Certificate
active
06380572
ABSTRACT:
BACKGROUND
The present disclosure relates, in general, to image sensors and, in particular, to silicon-on-insulator (SOI) active pixel sensors with the photosites implemented in the substrate.
In general, image sensors find applications in a wide variety of fields, including machine vision, robotics, guidance and navigation, and automotive applications, as well as consumer products. While complementary metal-oxide-semiconductor (CMOS) technology has provided the foundation for advances in low-cost, low-power, reliable, highly integrated systems for many consumer applications, charge coupled devices (CCDs) have been, until recently, the primary technology used in electronic imaging applications. CCDs, however, are high capacitance devices that require high voltage clocks, consume large amounts of energy, and provide only serial output. They require specialized silicon processing that is not compatible with CMOS technology.
More recently, the availability of near or sub-micron CMOS technology and the advent of active pixel sensors (APS) have made CMOS technology more attractive for imaging applications. Active pixel sensors have one or more active transistors within the pixel unit cell and can be made compatible with CMOS technologies.
In the past few years, small pixel sizes, low noise, high speed, and high dynamic range have been achieved in CMOS imagers. In addition, a wide variety of pixel architectures and designs that optimize various aspects of imager performance have been demonstrated using CMOS-based technology.
It is expected that scaling of MOS devices to smaller geometries will continue to yield higher operating speeds and greater packing densities in CMOS-based integrated circuits. While fine geometries are desirable for computers and other circuits, such scaling can adversely affect the performance of imagers. For example, the scaling of MOS devices in imagers requires a continued increase in channel doping, thus leading to significantly reduced depletion widths on the order of less than 0.1 micron (&mgr;m).
As shown in
FIG. 1
, a photosite is implemented using bulk-CMOS technology. In this context, “bulk-CMOS” technology refers to the fact that the substrate
20
is an integral part of the MOS devices. The photo-collection site is the reverse-biased photodiode
22
formed by the n+/p-substrate junction
24
. Photocarriers are stored at the n+/p interface where the potential is highest. Photoelectrons generated within the depletion region
26
are collected at the interface
24
with a high efficiency due to the existence of an electric field. On the other hand, only some of the photoelectrons generated outside the depletion region
26
will diffuse into the collecting area, thereby reducing the collection efficiency and increasing cross-talk.
For photons having a wavelength in the range of 400-800 nanometers (nm), the photon absorption depth varies from about 0.1 to 10 &mgr;m. However, in a typical 0.5 &mgr;m CMOS technology, the depletion widths are less than 0.2 &mgr;m. With the exception of blue light, many photons in the visible spectrum will be absorbed outside the depletion region
26
. Therefore, CMOS imagers implemented using a 0.5 &mgr;m technology will exhibit a lower quantum efficiency and increased cross-talk compared to imagers implemented with a coarser process. The increased cross-talk can lead to degraded color performance and smear. In addition to optical cross-talk, imagers made using bulk-CMOS technology also tend to exhibit electrical cross-talk.
Another problem in imagers made using bulk-CMOS technology is a rise in photodiode leakage current when the device is exposed to radiation. The rise in leakage current is caused by the use of Local Oxidation of Silicon (LOCOS) processes to create isolation regions
28
between active circuits. The “bird's beak”
30
feature at the transition between the thin-gate oxide region
32
and the thick field-oxide region creates a high electric field, thereby causing increased trap-generation during exposure to radiation. Although the leakage current can be reduced by using a radiation-hard fabrication process, such processes are relatively expensive and add to the overall cost of the imager.
In contrast to bulk-CMOS technology, SOI-CMOS technologies have recently been developed. In a SOI-CMOS process, a thick silicon substrate is separated from a thin silicon film by a buried oxide. The thin silicon film is patterned to produce the MOS devices. The principal of operation is similar to the operation of bulk-MOS devices, except the transistors do not share a common substrate.,
The thin-film nature of SOI-MOS devices and the absence of a common substrate can provide several advantages over bulk-MOS devices, including better performance for short channel devices, lower power and higher speed resulting from lower parasitic capacitance, and no latch-up. In addition, SOI-CMOS processes can provide higher device density, less leakage current and radiation hardness.
Nevertheless, the thin silicon film in SOI-MOS devices previously has made them unsuitable for imagers. In particular, the silicon film, with a thickness of only about 0.1-0.3 &mgr;m, is too thin to efficiently absorb visible light with photon depths of about 3-4 &mgr;m.
SUMMARY
In general, active pixel or other optical sensors that can be incorporated, for example, in a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film.
According to one aspect, a method of fabricating an active pixel sensor includes forming a photodetector in a silicon substrate and forming electrical circuit elements in a thin silicon film formed on an insulator layer disposed on the substrate. Interconnections among the electrical circuit elements and the photodetector are provided to allow signals sensed by the photodetector to be read out via the electrical circuit elements formed in the thin silicon film.
In a related aspect, a method of fabricating an active pixel sensor includes forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.
According to another aspect, an active pixel sensor includes a silicon substrate having a photodetector formed therein. An insulator layer is disposed on the silicon substrate. The pixel sensor also includes a readout circuit to read signals from the photodetector. The readout circuit includes electrical circuit elements formed in a thin silicon film disposed on the insulator layer.
One or more of the following features are present in some implementations. The photodetector can be, for example, a photodiode or photogate-type photodetector.
The electrical circuit elements formed in the thin silicon film can include multiple SOI-MOS transistors. The readout circuit may include a reset switch, a buffer switch and a row selection switch. For example, the buffer switch can comprise a source follower input transistor connected in series with the row selection switch so that when the row selection switch is turned on, a signal from the active pixel sensor is transferred to a column bus. In some embodiments, the reset switch includes a p-type MOS transistor.
In other implementations, the readout
Pain Bedabrata
Zheng Xinyu
California Institute of Technology
Fish & Richardson P.C.
Flynn Nathan
Forde Remmon R.
LandOfFree
Silicon-on-insulator (SOI) active pixel sensors with the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Silicon-on-insulator (SOI) active pixel sensors with the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon-on-insulator (SOI) active pixel sensors with the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2867158