Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
1996-11-12
2001-04-03
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S424000, C438S404000, C438S410000
Reexamination Certificate
active
06211039
ABSTRACT:
THE FIELD OF THE INVENTION
The present invention relates generally to methods and apparatus for isolating semiconductor devices with silicon-on-insulator technology, and more particularly, to forming isolated silicon islands.
BACKGROUND OF THE INVENTION
The advantages of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are well documented. Typically, SOI technology reduces undesired p-n junction capacitance between a source/drain and a substrate by approximately twenty-five-percent as compared to other conventional techniques for CMOS ICs. Furthermore, CMOS ICs fabricated with SOI technology have less active current consumption while maintaining device performance equivalent to that of similar devices formed on bulk-silicon substrates. Other advantages of SOI technology include suppression of the short channel effect, suppression of the body-effect, high punch-through immunity, and reduced latch-up and soft errors. As the demand increases for battery-operated equipment, SOI technology is becoming increasingly more popular due SOI device's low power requirements and high speeds.
There are many different techniques for isolating devices in ICs. A technique is selected based on various attributes, such as minimum isolation spacing, surface planarity, process complexity, and density of defects generated during fabrication.
SIMOX (Separation by Implanted Oxygen) technology is one method for forming SOI structures. SIMOX entails implanting a high dose of oxygen ions at a sufficiently deep level within a silicon substrate. A subsequent anneal step forms a buried oxide layer in the substrate. After the anneal step, an additional layer of epitaxial silicon is usually deposited to obtain a sufficiently thick silicon layer on which to form a device. Disadvantages of SIMOX include SIMOX's high expense and yield loss, which undesirably decreases achievable chip density.
Wafer bonding is another technique for forming an isolation layer in a substrate. In wafer bonding, two oxidized silicon wafers are fused together in a high-temperature furnace. However, wafer bonding undesirably increases the substrate thickness. Furthermore, wafer bonding techniques are often plagued by low production yield due to particles/voids, which prevent adequate bonding between the two wafers in such areas.
Forming silicon islands through a series of etch and oxidation steps is another technique used for forming an isolation layer in a substrate. For example, the Sobczak U.S. Pat. No. 4,604,162 uses a series of a pad oxide layer, a silicon nitride layer, and a silicon dioxide layer, which are photolithographically masked and anisotropically etched to define silicon islands capped with a silicon nitride layer. Then, a second anisotropic etch, such as a reactive ion etch (RIE), removes further substrate material between the silicon islands. The depth of the second anisotropic etch is proportional to the width of the silicon islands. A subsequent oxidation step forms silicon dioxide, undercutting the silicon islands and isolating each of them from surrounding regions.
The etch and oxidation technique described in the Sobczak patent has not been used commercially because it is too costly and consumes too much time to oxidize an area having an effective width as great as that of the feature size. Furthermore, another disadvantage of the method described in the Sobczak patent is that the resulting isolated silicon structure is afflicted with excess mechanical stress and crystal damage at the silicon/oxide interface. The mechanical stress and crystal damage is created due to the volume expansion of thermal oxide during its formation. Typically, the volume of oxide formed is approximately twice that of the silicon consumed in forming the oxide. While thermally growing oxide to undercut the silicon structures, until the silicon structure is completely isolated, the remaining silicon filament connecting the silicon island to the bulk substrate is under considerable tensile stress. Such tensile stress can only be accommodated by the generation and propagation of dislocations. Such dislocations will propagate toward the silicon oxide interface, giving rise to such deleterious electrical effects as high junction leakage and low carrier mobility.
Thus, there is a need for an effective isolation technique that minimizes the generation of dislocations during the isolation process. Such dislocations can potentially degrade device performance. Furthermore, an isolation technique is needed, which allows fabrication of highly dense ICs without increasing the dimensions of the IC.
SUMMARY OF THE INVENTION
The present invention provides a method for forming silicon-on-insulator (SOI) islands on a supporting silicon substrate for subsequent semiconductor device formation. The present invention also provides for SOI structures formed with the method of the invention. In general, fully undercut silicon islands are formed in the silicon substrate, supported by lateral silicon oxide bars extending to the silicon substrate. Silicon oxide is then formed between the silicon islands and the silicon substrate.
In one embodiment of the present invention, the islands are formed by directionally-etching a first set of trenches in a silicon substrate through a blanket pad structure to laterally isolate bars of silicon. Silicon oxide is then formed in the first set of trenches. Next, a second set of trenches is directionally-etched through the blanket pad structure in an orthogonal direction to the first set of trenches. Then, silicon nitride is deposited over the trenches, extending down the sidewalls. An isotropic chemical etch is then used to fully undercut and vertically isolate the laterally-isolated bars of silicon in the substrate. The etch-evacuated regions are filled with an isolating oxide to complete the SOI structure. The isolating oxide used to fill the etch-evacuated regions is a combination of thermal oxide and chemical vapor deposition (CVD) oxide.
The resulting SOI structure formed according to the present invention comprises a plurality of silicon islands in a silicon substrate. Chemical vapor deposition silicon oxide extends from the top of the SOI structure to the silicon substrate, vertically isolating the silicon islands. Thermal silicon oxide extends between the silicon islands and the silicon substrate, horizontally isolating the silicon islands.
Resulting SOI structures, formed with the method of the present invention, have a minimum amount of mechanical stress and crystal damage at the silicon/oxide interface because silicon filaments do not connect the silicon islands to the bulk substrate during thermal oxidation. Thus, compressive stress resulting from volume expansion of the growing oxide between the silicon filament and growing oxide is eliminated. As integrated circuits are becoming more dense, it is important to minimize such imperfections in devices to optimize electrical performance. The method of this invention is also compatible with forming SOI structures, without decreasing achievable device density as do the wafer bonding and SIMOX methods.
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Auberton-Herve, A.J., “SOI:
Blum David S
Bowers Charles
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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