Silicon on insulator field effect transistors having shared...

Details Silicon on insulator field effect transistors having shared... Silicon on insulator field effect transistors having shared...

2000-04-12

2003-09-23

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000, C257S350000, C257S369000

Reexamination Certificate

active

06624459

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit and, more particularly to very large scale integrated (VLSI) circuits wherein field effect transistors (FETs) are formed in a surface layer of a silicon on insulator (SOI) chip.
2. Background Description
Bulk silicon field effect transistors (FETs) are formed on the surface of a silicon chip or wafer. In what is typically referred to as CMOS technology, the silicon wafer or substrate may be of one conduction type, e.g., P-type, and areas or wells of a second conduction type, e.g., N-type, are formed in the P-type wafer. N-type FETs (NFETs) are formed on the surface of the P-type wafer and P-type FETs (PFETs) are formed on the surface of the N-wells. A first bias voltage, typically zero Volts (0V) or ground (GND), is applied to the substrate to bias the NFETs and a second bias voltage, typically the supply voltage (V
hi
), is applied to the N-wells. The substrate and N-well bias voltages help to stabilize respective FET electrical characteristics, including improving threshold voltage (V
t
) and device current stability. Changing a device bias changes device characteristics, increasing/decreasing device V
t
and decreasing/increasing device operating current depending upon the magnitude and direction of the respective change.
Performance improvements for these prior art bulk transistor technologies has been achieved, normally, by reducing feature size or “scaling.” In addition to scaling, more recently, silicon on insulator (SOI) technology has become the main source of performance improvement for transistors.
FIG. 1
shows a cross section
100
of a prior art SOI wafer through a pair of transistors
102
,
104
that may be NFETs or PFETs. The FETs
102
,
104
are formed in a thin silicon surface layer
106
that is isolated from an underlying silicon substrate
108
by a buried oxide (BOX) layer
110
. In a typically complex series of mask steps, SOI islands
112
are formed in the silicon surface layer
106
by etching shallow trenches through the surface layer
106
and filling the shallow trenches with oxide
114
to isolate islands
112
from each other. This type of isolation is normally referred to as Shallow trench isolation (STI). STI is used to isolate circuits formed on the islands from each other and, also, isolate the FETs forming the circuits from each other.
After forming a gate oxide layer on the surface of the silicon islands
112
, gates
116
are patterned and formed at the location of devices
102
,
104
. Source/drain regions
118
are defined using a standard implant and diffusion step, after forming lightly doped diffusion regions
120
at the gate boundaries, if desired. Metal contacts
122
are selectively formed at source/drain regions
118
. Device channels
124
,
126
are completely isolated from other channels by source/drain diffusions
118
at either end, BOX layer
110
below, gate oxide above and STI (not shown) along the sides of the channel.
Ideally, the thin silicon surface layer
106
is no thicker than what is necessary to form a channel
124
,
126
between a pair of source/drain diffusions
118
. However, in practice, the silicon surface layer is thicker than the depth of the FET's channel inversion layer. So, when the channel inversion layer forms, i.e., when the FET is turned on, an uninverted layer remains beneath the channel inversion layer. This uninverted layer remains isolated, resistively, from adjacent regions and any charge that is introduced into the uninverted channel region remains trapped there until it leaks out through junction leakage or is otherwise coupled out. This trapped charge can produce unwanted device channel bias resulting in what is referred to as body effects that are localized to an individual device.
So, these prior art SOI FETs
102
,
104
have isolated floating channels
124
,
126
that are not biased by any bias voltage. Thus, the channel bias of any device is dependent upon its current operating state and the device's history, i.e., any remaining charge that has been previously introduced through capacitive coupling or bipolar injection. For typical individual logic circuits such as, decoders, clock buffers, input or output drivers and array output drivers, slight variations in device characteristics that result from floating device channels, may be negligible, neglectable and given little consideration.
However, these localized body effects and other sporadically occurring parasitic bipolar effects, i.e., at source/drain diffusion junctions, are serious design problems for densely packed SOI circuits such as for example, memory arrays. Body effects occur as a particular device switches because charge is capacitively coupled into/out of the floating channel area. Bipolar effect current may add charge to the floating channel. Further, charge in any particular device may vary as the chip operates because individual devices switch somewhat independently of each other. As noted above, FET device characteristics are dependent upon device substrate voltage. Repetitively accessing a random access memory (RAM) cell, both to read and to write it, unintentionally induces local body effects in some cell devices.
For prior art SOI SRAMs, these body effects change device thresholds and modulate device currents for affected devices reducing the signal stored in the cell as well as the signal passed by cell access transistors. These local effects can cause the SRAM cell to favor one state over the other, resulting in sporadic read upsets with no apparent reason. An imbalance in cell pass gates may increase cell write time and sense time. As a result, intermittent problems may arise, such as spuriously reading the wrong data or, random cell failures. These types of intermittent problems are notoriously difficult to identify and diagnose. So, channel bias variations from body effects causes device non-uniformities that result in difficult to identify sporadic chip failures sometimes characterized as “soft failures.”
Thus, there is a need for improving SOI RAM stability.
PURPOSES OF THE INVENTION
It is a purpose of this invention is to improve memory cell stability;
It is another purpose of the invention to improve static random access memory (SRAM) cell tolerance to local body effects;
It is yet another purpose of the invention to improve SRAM cell tolerance to local body effects while maintaining cell density.
SUMMARY OF THE INVENTION
The present invention is a silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid SOI/bulk structure wherein the source/drain diffusions do not penetrate to the underlying insulator layer, resulting in a FET in the surface of an SOI layer with a body or substrate contact formed at a shared contact. FETs are formed on SOI silicon islands located on a BOX layer and isolated by shallow trench isolation (STI). NFET islands in the SRAM cells include a body contact to a P-type diffusion in the NFET island. Each NFET in the SRAM cells include at least one shallow source/drain diffusion that is shallower than the island thickness. A path remains under the shallow diffusions between NFET channels and the body contact. The P-type body contact diffusion is a deep diffusion, the full thickness of the island. Bit line diffusions shared by SRAM cells on adjacent wordlines may be deep diffusions.


REFERENCES:
patent: 5767549 (1998-06-01), Chen et al.
patent: 5774411 (1998-06-01), Hsieh et al.
patent: 6194763 (2001-02-01), Hisamoto et al.
patent: 6344671 (2002-02-01), Mandelman et al.
Kuang et al., “SRAM Bitline Circuits on PD SOI: Advantages and Concerns,” 32IEEE J. of Solid-State Circuits6 (Jun. 1997).
Chuang, C. T., “Design Considerations of SOI Digital CMOS VLSI,”Proceedings 1998 IEEE International SOI Conference(Oct. 1998).

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