Silicon on insulator field effect transistor with...

Details Silicon on insulator field effect transistor with... Silicon on insulator field effect transistor with...

2001-07-10

2004-07-06

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

C438S459000, C438S406000

Reexamination Certificate

active

06759308

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to the design of field effect transistors (FETs) and, more particularly to a static induction type FET with a heterojunction gate formed on a silicon on insulator (SOI) wafer.
BACKGROUND OF THE INVENTION
Conventional or bulk semiconductor devices are formed in semiconductive material by implanting a well of either P-type or N-type conductivity silicon in a silicon substrate wafer of the opposite conductivity. Gates and source/drain diffusions are then manufactured using commonly known processes. These form devices known as metal-oxide-semiconductor (MOS) field effect transistors (FETs). When a given chip uses both P-type and N-type, it is known as a complimentary metal oxide semiconductor (CMOS). Each of these transistors must be electrically isolated from the others in order to avoid shorting the circuits. A relatively large amount of surface area is needed for the electrical isolation of the various transistors. This is undesirable for the current industry goals for size reduction. Additionally, junction capacitance between the source/drain and the bulk substrate increase power consumption, require higher threshold voltages, and slows the speed at which a device using such transistors can operate (e.g. degrades frequency response). These problems result in difficulties in reducing the size, power consumption, and voltage of CMOS technology devices.
In order to deal with the junction capacitance problem and improve frequency response, silicon on insulator technology (SOI) has been gaining popularity. A SOI wafer is formed from a bulk silicon wafer by using conventional oxygen implantation techniques to create a buried oxide layer at a predetermined depth below the surface. The implanted oxygen oxidizes the silicon into insulating silicon dioxide in a guassian distribution pattern centered at the predetermined depth to form the buried oxide layer.
An SOI field effect transistor comprises two separated regions consisting of the source and drain regions of the transistor of a first semiconductor conductivity and a channel region between them of the opposite semiconductor conductivity covered by a thin gate insulator and a conductive gate. Conduction in the channel region normally occurs immediately below the gate insulator in the region in which depletion can be controlled by the gate voltage.
A problem associated with reducing the size of an SOI FET structure is a reduction in the length of the channel (distance between the source region and the drain region) degrades FET performance because of a phenomenon known as the short channel effect. More specifically, the decreased channel length permits depletion regions adjacent to the source region and the drain region to extend towards the center of the channel which increases the off state current flow through the channel (current flow when the gate potential is below threshold) and the reduced channel width tends to decrease current flow when the gate potential is above threshold.
Accordingly, there is a strong need in the art for a silicon on insulator field effect transistor structure which can be scaled to sub-micron dimension without significant performance degradation.
SUMMARY OF THE INVENTION
A first object of this invention is to provide a transistor structure. The structure comprises a central channel region comprising a first semiconductor lightly doped with a first impurity element to increase first conductivity free carriers and a source region and a drain region, on opposing sides of the central channel region. Both the source region and the drain region are also of the first semiconductor material heavily doped with the first impurity element. A gate, adjacent the channel region and forming a heterojunction with the channel region, is comprised of the first semiconductor and a second semiconductor, with an energy gap greater than the first semiconductor, and is doped with a second impurity element to increase carriers of the opposite conductivity as the first free carriers.
The transistor structure also includes a backgate which is adjacent to the channel region and on an opposing side of the channel region from the gate. The backgate also forms a heterojunction with the channel region and comprises the first semiconductor and the second semiconductor and is doped with the second impurity element.
The first semiconductor may be silicon and the second semiconductor may be carbon such that the gate and the backgate are a silicon carbide crystal structure. The first impurity may be a donor impurity such as arsenic and the second impurity may be a receptor impurity such as boron such that the first conductivity free carriers may be electrons and the second conductivity free carriers may be holes.
A second aspect of the present invention is to provide a silicon on insulator transistor structure. The structure comprises an insulating oxide layer separating a device layer of semiconductor material from a bulk semiconductor base region. A generally rectangular central channel region within the device layer semiconductor material is doped with a first impurity element to increase first conductivity free carriers. A source region and a drain region are positioned on opposing sides of the generally rectangular central channel region. Both the source region and the drain region comprise the device layer semiconductor material heavily doped with the first impurity element. A gate, adjacent the channel region and forming a heterojunction with the channel region, comprises the device layer semiconductor and a second semiconductor, with an energy gap greater than the device layer semiconductor, and is doped with a second impurity element to increase carriers of the opposite conductivity as the first free carriers.
The silicon on insulator transistor structure also includes a backgate which is adjacent to the channel region and on an opposing side of the channel region from the gate. The backgate also forms a heterojunction with the channel region and comprises the device layer semiconductor material and the second semiconductor and is doped with the second impurity element.
The device layer semiconductor may be silicon and the second semiconductor may be carbon such that the gate and the backgate are a silicon carbide crystal structure. The first impurity may be a donor impurity such as arsenic and the second impurity may be a receptor impurity such as boron such that the first conductivity free carriers may be electrons and the second conductivity free carriers may be holes.
A third aspect of the present invention is to provide a method of controlling the flow of electricity between a source semiconductor region and a drain semiconductor region in a transistor. Both the source semiconductor region and the drain semiconductor region are heavily doped with a first impurity element. The method comprises: a) positioning a generally rectangular central channel region between the source region and the drain region, the channel region lightly doped with the first impurity element to increase free carriers of a first type; b) positioning a gate adjacent the channel region and extending along a side of the central channel region adjacent the source region and forming a junction with the channel region, the gate comprising the semiconductor and a second semiconductor with an energy gap greater than the first semiconductor and being doped with a second impurity element to increase free carriers opposite of the first type; and c) varying the potential of the gate region relative to the source region to control depletion within the channel region.
The method may further include positioning a backgate adjacent the channel region, and on an opposing side of the channel region from the gate, and forming a junction with the channel region, the backgate comprising the first semiconductor and a second semiconductor with an energy gap greater than the first semiconductor and being doped with a second impurity element to increase free carriers opposite of the first type and varying the potential

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