Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-25
2004-11-09
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S351000, C257S369000, C257S386000, C257S509000, C257S545000
Reexamination Certificate
active
06815771
ABSTRACT:
The disclosure of Japanese Patent Application No. 2001-330276 filed on Oct. 29, 2001 including the specification, drawings and abstract is incorporated herein by reference in its entirety
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to semiconductor devices fabrication on silicon on insulator (SOI) substrates and to layout methods for such semiconductor devices.
2. Description of Related Art
Plasma etching, sputtering, plasma chemical vapor deposition (i.e., plasma CVD), ion implantation and other plasma processes are widely employed in fabrication of semiconductor devices.
During the plasma process, the surface of the semiconductor substrate is irradiated with charged particles (i.e., ions an electrons) in the plasma. When the semiconductor substrate has a metal wire on its surface, which is not connected to the substrate, electric charges enter and accumulate in the metal wire. In other words, a wire on the surface of the substrate acts as an antenna to collect charges from the plasma.
Such accumulated charges induce charging-up and cause damage to the devices. For example, if a gate electrode of a metal-oxide-semiconductor (MOS) device (MOS transistor) is connected to the metal wire, a gate insulating film below the gate electrode may be damaged. That is, a high voltage due to the charging up is applied to the gate insulating film and thereby degrades the quality of the semiconductor device and, further, causes dielectric breakdown.
Because the amount of accumulated charge increases in proportion to the area of the wire, the voltage applied to the gate insulating film also increases in proportion to the ratio of the area of the wire to the area of the gate insulating film. Therefore, when the ratio of the area of the wire to the area of the gate insulating film, or an “antenna ratio”, exceeds a certain threshold value, the gate insulating film will be damaged.
Therefore, in the layout of semiconductor devices including MOS transistors, it is proposed to limit the antenna ratio between the area of the wire and that of the gate insulating film to be less than a predetermined value so that the gate insulating film is not damaged during a plasma process. For example, Japanese Unexamined Patent Publications Hei 8-97416 (U.S. Pat. No. 5,744,838), Hei 11-186394, and Hei 11-297836 (U.S. Pat. No. 6,421,816) disclose such method.
On the other hand, silicon on insulator (SOI) devices, in which MOS transistors are fabricated in an active layer on an insulating substrate, have been increasingly used in recent years. However, detailed investigation of an influence of the plasma process to the SOI device has not been reported.
SUMMARY OF THE INVENTION
Through extensive experimentations, this inventor has discovered that a different kind of antenna ratio should be taken into account in the layout of SOI devices. That is, different from the ratio between an area of a wire and a area of gate insulating film, which is known to determine the influence of plasma processes on conventional semiconductor devices, this inventor has discovered that a ratio between an area of a wire and an area of doped region, such as a source/drain region of a MOS transistor, mainly determine the influence on SOI devices.
In various exemplary embodiments according to the invention, a semiconductor device can include a silicon on insulator substrate having an active layer, at least one doped region formed in the active layer and that constitutes a source/drain region of a MOS transistor and an antenna wire formed in an antenna wiring layer. The antenna wire is electrically connected to the at least one doped region directly or through at least one connecting wire in at least one lower wiring layer below the antenna wiring layer. Moreover, a ratio of a total area of the antenna wire to a total area of the at least one doped region is limited within a range so that one of plasma processes to pattern the antenna wiring layer and to deposit an interlayer dielectric film covering the antenna wiring layer does not damage the MOS transistor.
The “antenna wiring layer” may be any one of wiring layers in the semiconductor device that is exposed to plasma during the fabrication of the device.
In various exemplary embodiments according to another embodiment of the invention, a semiconductor device can include a silicon on insulator substrate having an active layer, at least one doped region formed in the active layer and that constitutes a source/drain region of a MOS transistor, and an antenna wire formed in an antenna wiring layer. The antenna wire is electrically connected to the at least one doped region directly or through at least one connecting wire in at least one lower wiring layer below the antenna wiring layer. Moreover, an interlayer dielectric film that covers the antenna wiring layer having at least one connection hole for connecting to the antenna wire can be included. A ratio of a total area of the at least one connection hole to a total area of the at least one doped region is limited within a range so that a plasma process to form the connecting hole does not damage the MOS transistor.
In various exemplary embodiments according to another embodiment of the invention, a semiconductor device can include a silicon on insulator substrate having an active layer, at least one doped region formed in the active layer and an antenna wire formed in an antenna wiring layer. The antenna wire is electrically connected to the at least one doped region directly or through at least one first connecting wire in at least one lower wiring layer below the antenna wiring layer. Furthermore, a dummy doped region can be formed in the active layer electrically connected to the doped region through at least one second connecting wire in the antenna wiring layer and/or in the at least one lower wiring layer.
In various exemplary embodiments according to another embodiment of the invention, a layout method of a semiconductor device can include the steps of placing at least one doped region in an active layer of a silicon on insulator substrate, and placing an antenna wire in an antenna wiring layer electrically connected to the at least one doped region directly or through at least one first connecting wire in at least one lower wiring layer below the antenna wiring layer. The layout method can further include, when a ratio of a total area of the antenna wire to a total area of the at least one doped region exceeds a predetermined value, performing at least one of: (a) adding a dummy doped region in the active layer electrically connected to the doped region through at least one second connecting wire in the antenna wiring layer and/or in the at least one lower wiring layer; (b) adding a junction diode electrically connected to the doped region through at least one second connecting wire in the antenna wiring layer and/or in the at least one lower wiring layer; (c) dividing the antenna wire into two parts and electrically connecting the two parts through a third connecting wire in an upper wiring layer above the antenna wiring layer; and (d) dividing one of the antenna wire and the at least one first connecting wire into two parts, and inserting a buffer between the two parts.
In various exemplary embodiments according to another embodiment of the invention, a layout method of a semiconductor device can include the steps of placing at least one doped region in an active layer of a silicon on insulator substrate, placing an antenna wire in an antenna wiring layer electrically connected to the at least one doped region directly or through at least one first connecting wire in at least one lower wiring layer below the antenna wiring layer, and placing at least one connection hole for connecting to the antenna wire. The layout method can further include, when a ratio of a total area of the at least one connection hole to a total area of the at least one doped region exceeds a predetermined value, performing at least one of: (a) adding a dummy doped region in the active layer electrically connected to the doped
Fenty Jesse A.
Jackson Jerome
Kawasaki Microelectronics Inc.
Oliff & Berridg,e PLC
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