Silicon nitride dopant diffusion barrier in integrated circuits

Details Silicon nitride dopant diffusion barrier in integrated circuits Silicon nitride dopant diffusion barrier in integrated circuits

1998-06-10

2001-08-21

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S195000, C438S196000, C438S399000, C438S587000, C438S621000, C438S706000, C438S738000, C438S743000, C438S744000, C438S791000

Reexamination Certificate

active

06277720

ABSTRACT:

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
This invention is in the field of semiconductor integrated circuits, and is more specifically directed to the manufacture of such integrated circuits.
Recent advances in the field of integrated circuit processing continue to greatly increase device densities, and thus the functionality, of integrated circuit devices. For example, metal-oxide semiconductor field-effect transistor (MOSFET) channel lengths of 0.50&mgr; and smaller are now commonplace in very large scale integration (VLSI) integrated circuit devices such as dynamic random access memories (DRAMs) and microprocessors. The continued scaling of photolithographic critical dimensions (i.e., widths of patterned conductive elements and contacts) to achieve these high device densities also require scaling of element thicknesses; in particular, junction depths in MOSFET transistors with 0.5&mgr; channel lengths and smaller are typically on the order of 0.30&mgr;.
In addition to these extremely small device dimensions now being used in modern integrated circuits, multiple levels of conductors are now used to interconnect the ever-increasing number of active devices, and thus obtain the highly integrated functionality. For example, three levels of metal interconnection, in addition to lower level polysilicon-based gate level interconnects, are now common in VLSI circuits such as DRAMs and microprocessors. These multiple levels of metal interconnection not only increase the complexity of contact placement and location, but also necessitate the formation of highly planar top surfaces of insulating layers, to permit the deposition of high integrity metal films (i.e., without discontinuities at steps). In addition, the planarization of films has recently become essential in the patterning of the metal films and contact openings, due to the limited depth of field provided by conventional photolithographic equipment of submicron resolution.
In addition to multiple levels of metalliation, insulating layers with highly planar surfaces are also necessary for complex capacitor structures as used in modern DRAMs. For example, the fabrication of capacitor structures that in part overlie planarized insulating layers, is known in the art. Attention is directed in this regard to commonly assigned copending application Ser. 08/845,755, filed Apr. 25,1997, entitled “A Silicon Nitride Sidewall and Top Surface Layer Separating Conductors”for a description of the fabrication of such capacitors in a DRAM integrated circuit
As is fundamental in the art, chemical vapor deposition of doped silicon dioxide is commonly used to form insulating layers in semiconductor integrated circuits. These oxide films are typically doped with both phosphorous and boron, and as such are commonly referred to as “BPSG”, for boro-phospho-silicate glass. Doped oxide films are particularly attractive in the formation of oxide films with planar top surfaces, as the presence of the dopants in silicon dioxide causes these films to flow (i.e., “reflow”) and densify when subjected to a high temperature anneal. As such, BPSG films are commonly used as planarized insulating films, particularly to underlie a metal conductor layer.
Referring first to
FIG. 1
, a cross-section of a conventional integrated circuit will now be described. In this example, both p-channel MOSFETs and n-channel MOSFETs are utilized, and as such the conventional integrated circuit of
FIG. 1
is fabricated according to complementary-MOS (CMOS) technology. Substrate
2
is p-type in this example. N-channel transistors are formed within a double well structure that includes n-type deep well
3
, within which lightly-doped p-type well
9
is formed; conversely, p-channel transistors are formed within lightly-doped n-type well
4
. The integrated circuit of
FIG. 1
is a dynamic random access memory in this example, in which p-well
9
defines the location of memory cells, and n-well
4
defines the location of p-channel periphery transistors; n-channel periphery transistors will also be implemented in similar fashion as those in wells
3
,
9
, but are not shown in
FIG. 1
for the sake of clarity. Field oxide structures
5
, formed by LOCOS (local oxidation of silicon) serve as source/drain isolation in the usual manner.
Gate structures
10
are disposed at various locations of the surface of the structure, and are constructed in the usual manner, overlying gate oxide layer
8
to define the channel region of the transistor devices. In modern high-performance integrated circuits, gate structures
10
are fabricated as multilayer structures of polysilicon and a metal silicide, such as tungsten disilcide, to provide the necessary conductivity, particularly in gate structures
10
of submicron widths. P-type source/drain regions
6
and n-type source/drain regions
7
are formed into their respective wells
4
,
9
, in a self-aligned manner relative to. gate structures
10
as is conventional in the art. In this example, each of gate structures
10
include, sidewall filaments
11
, formed of an insulating material such as silicon dioxide or silicon nitride; sidewall filaments
11
are used to define lightly-doped source/drain extension
6
′,
7
′ thereunder, as shown in FIG.
1
.
In the example of
FIG. 1
, planarizing silicon dioxide film
14
is disposed over the surface of the structure, with undoped oxide film
12
disposed therebeneath. Undoped oxide film
12
, in this conventional example, is formed by way of chemical vapor deposition utilizing the decomposition of tetraethyloxysilane (TEOS), to a thickness of on the order of 500 Å, and is conformal to the various structures (e.g., gate structures
10
, sidewall filaments
11
, and field oxide structures
5
). Planarizing oxide film
14
, on the other hand, is deposited by way of CVD with phosphorous and boron, to a thickness of on the order of 5000 Å. Following deposition, the structure is subjected to a high temperature anneal to reflow and densify BPSG film
14
; an etchback is then performed to planarize BPSG film
14
as illustrated in FIG.
1
.
Following the processing described hereinabove to form the structure illustrated in
FIG. 1
, contact openings are then typically defined by way of photolithography and etched through films
12
,
14
to expose locations of gate structures
10
, and source/drain regions
6
,
7
to which contact is desired to be made. The surface of BPSG film
14
is then suitable for deposition of a metal conductor layer thereover, either making contact itself through the etched contact openings, or by way of conductive plugs of polysilicon or refractory metal that may be first formed into the contact openings.
The purpose of undoped oxide film
12
is to serve as a barrier to boron and phosphorus dopant contained within BPSG film
14
, preventing the diffusion of these species into source/dram regions
6
,
7
as may occur in subsequent high temperature processes as reflow of BPSG film
14
and the like. As is fundamental in the art, diffusion of dopant from BPSG film
14
into the active devices is undesirable, as excess boron and phosphorous will either counterdope source/drain regions
6
,
7
(for diffusing dopant of opposite conductivity type) or drive deeper the junctions of source/drain regions
6
,
7
. Each of these effects reduce device performance significantly, either through increasing source/drain resistance, or through increasing junction capacitance.
In addition, diffusion of dopant from BPSG film
14
is also deleterious to film
14
itself. In particular, voids in BPSG film
14
have been observed, and are believed to be caused to diffusion of phosphorous out of the film. Such voids are, of course, hazards to yield and reliability of the integrated circuit.
As device sizes are scaled smaller, however, it has been observed that undoped oxide film
12
is incapable of preventing dopant diffusion from BPSG film
14
, especially as its thickness falls much below
500
A. Incre

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