Silicon layer with high resistance and fabricating method...

Details Silicon layer with high resistance and fabricating method... Silicon layer with high resistance and fabricating method...

2005-06-07

2008-09-16

Nguyen, Tuan H (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S364000

Reexamination Certificate

active

07425736

ABSTRACT:
A silicon layer with high resistance is provided. The silicon layer with high resistance is positioned on a substrate. Also, the silicon layer with high resistance includes a plurality of silicon material layers, and an interface layer between every two of the silicon material layers, wherein, the silicon material layers and the interface layer have dopants therein. The amount of implanted dopants is about 1*1014˜5*1015ions/cm2, and the silicon material layers have different grain boundaries.

REFERENCES:
patent: 5298436 (1994-03-01), Radosevich et al.
patent: 5332689 (1994-07-01), Sandhu et al.
patent: 5587696 (1996-12-01), Su et al.
patent: 6610361 (2003-08-01), Heuer et al.

Affiliated with

Also associated with

Rating

Silicon layer with high resistance and fabricating method... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Silicon layer with high resistance and fabricating method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon layer with high resistance and fabricating method... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3990486