Silicon interposer with optical connections

Details Silicon interposer with optical connections Silicon interposer with optical connections

2001-08-22

2004-11-23

Coleman, William David (Department: 2823)

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

Packaging or treatment of packaged semiconductor

C438S108000

Reexamination Certificate

active

06821802

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to a silicon interposer with optical connections.
BACKGROUND OF THE INVENTION
There is a growing desire for “system on a chip” as integrated circuit technology makes steady progress and revolutionizes our daily life. Ideally, we would like to build a computing system by fabricating all the necessary integrated circuits on one wafer, as compared with today's method of fabricating many chips of different functions and packaging them to assemble a system. The concept of “system on a chip” has been around for a long time, but in practice, it is very difficult with today's technology to implement such a truly high-performance system because of vastly different fabrication processes and different manufacturing yields for the logic and memory circuits. To overcome some of these problems, Intel demonstrated a high-performance microprocessor and cache core based on a silicon-on-silicon multichip module technology. This technology was designed to have low interconnect parasitics and low cost. A 40 to 50% clock rate improvement was realized over a conventional packaging approach. More recently, a “system module” has recently been introduced. The module consists of two chips (logic and memory) with Chip A stacked on Chip B in a structure called Chip-on-Chip (COC) using a micro bump bonding technology (MBB). For high-performance computing systems, it is highly desirable for the microprocessor and memory devices to be located with close proximate for faster communication (high bandwidth). This leads to the consideration of very large chips and attendant lower wafer yield and productivity. However, even the largest chips which can be economically produced in any lithographic generation can contain only a relatively very small system. Therefore, in the foreseeable future, rather than building a truly integrated chip, the present trend of packaging several chips on a module will continue, but with the level of integration, on a given chip, being in part determined by the packaging capabilities. It will also be desirable to package chips in closer proximity to achieve higher performance. Another important objective is too reduce the energy required per switching event in driving circuits on the module.
SUMMARY OF THE INVENTION
The above mentioned problems with integrated circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification. An electronic packaging assembly which accords these benefits is provided.
In particular, an improved electronic packaging assembly is provided for increasing the operational bandwidth between different circuit devices, e.g. logic and memory chips, without requiring changes in current CMOS processing techniques. The electronic packaging assembly includes the use of a silicon interposer. The silicon interposer can consist of rejected wafers recycled from front-end semiconductor processing. This provides the added advantage of low cost and availability. A silicon interposer is thermally matched to the circuit devices such that coefficient of expansion mismatches are nonexistent. And, deposition of conductors on the silicon interposer's surface is readily accomplished using a standard integrated circuit multi-layer metallurgy.
The electronic packaging assembly also includes at least one, or a number of, semiconductor chips located on opposing surfaces of the silicon interposer. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various integrated circuit devices located on the opposing surfaces of the silicon interposer. An optical detector and an optical emitter are located on the silicon interposer and couple the silicon interposer to a fiber optical network. Improved performance in the form of higher bandwidth and a lower required energy per switching event is provided by this novel electronic packaging assembly.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.


REFERENCES:
patent: 3923567 (1975-12-01), Lawrence
patent: 3959047 (1976-05-01), Alberts et al.
patent: 3982268 (1976-09-01), Anthony et al.
patent: 4081701 (1978-03-01), White, Jr. et al.
patent: 4394712 (1983-07-01), Anthony
patent: 4595428 (1986-06-01), Anthony et al.
patent: 4631636 (1986-12-01), Andrews
patent: 4653025 (1987-03-01), Minato et al.
patent: 4710798 (1987-12-01), Marcantonio
patent: 4713841 (1987-12-01), Porter et al.
patent: 4739446 (1988-04-01), Landis
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 4977439 (1990-12-01), Esquivel et al.
patent: 5061987 (1991-10-01), Hsia
patent: 5079618 (1992-01-01), Farnworth
patent: 5153814 (1992-10-01), Wessely
patent: 5168334 (1992-12-01), Mitchell et al.
patent: 5229327 (1993-07-01), Farnworth
patent: 5258648 (1993-11-01), Lin
patent: 5275001 (1994-01-01), Yokotani et al.
patent: 5313361 (1994-05-01), Martin
patent: 5317197 (1994-05-01), Roberts
patent: 5343366 (1994-08-01), Cipolla et al.
patent: 5352998 (1994-10-01), Tamino
patent: 5362976 (1994-11-01), Suzuki
patent: 5392407 (1995-02-01), Heil et al.
patent: 5409547 (1995-04-01), Watanabe et al.
patent: 5415699 (1995-05-01), Harman
patent: 5432823 (1995-07-01), Gasbarro et al.
patent: 5438224 (1995-08-01), Papageorge et al.
patent: 5468681 (1995-11-01), Pasch
patent: 5532506 (1996-07-01), Tserng
patent: 5567654 (1996-10-01), Beilstein, Jr. et al.
patent: 5574923 (1996-11-01), Heeb et al.
patent: 5587119 (1996-12-01), White
patent: 5598031 (1997-01-01), Groover et al.
patent: 5598039 (1997-01-01), Weber
patent: 5610366 (1997-03-01), Fleurial et al.
patent: 5618752 (1997-04-01), Gaul
patent: 5622875 (1997-04-01), Lawrence
patent: 5633962 (1997-05-01), Kurata
patent: 5637828 (1997-06-01), Russell et al.
patent: 5646067 (1997-07-01), Gaul
patent: 5656548 (1997-08-01), Zavracky et al.
patent: 5657481 (1997-08-01), Farmwald et al.
patent: 5682062 (1997-10-01), Gaul
patent: 5692558 (1997-12-01), Hamilton et al.
patent: 5699073 (1997-12-01), Lebby et al.
patent: 5699291 (1997-12-01), Tsunemine
patent: 5714791 (1998-02-01), Chi et al.
patent: 5747728 (1998-05-01), Fleurial et al.
patent: 5753529 (1998-05-01), Chang et al.
patent: 5767001 (1998-06-01), Bertagnolli et al.
patent: 5781746 (1998-07-01), Fleck
patent: 5786628 (1998-07-01), Beilstein, Jr. et al.
patent: 5807783 (1998-09-01), Gaul et al.
patent: 5821624 (1998-10-01), Pasch
patent: 5834799 (1998-11-01), Rostoker et al.
patent: 5855735 (1999-01-01), Takada et al.
patent: 5861666 (1999-01-01), Bellaar
patent: 5901050 (1999-05-01), Imai
patent: 5902118 (1999-05-01), Hubner
patent: 5903018 (1999-05-01), Shimawaki
patent: 5903045 (1999-05-01), Bertin et al.
patent: 5915167 (1999-06-01), Leedy
patent: 5990550 (1999-11-01), Umezawa
patent: 5990564 (1999-11-01), Degani et al.
patent: 5991161 (1999-11-01), Samaras et al.
patent: 6016256 (2000-01-01), Crane, Jr. et al.
patent: 6137164 (2000-10-01), Yew et al.
patent: 6219237 (2001-04-01), Geusic et al.
patent: 6223273 (2001-04-01), Kanekawa et al.
patent: 6281042 (2001-08-01), Ahn et al.
patent: 4-133472 (1992-05-01), None
patent: 05-129666 (1993-05-01), None
patent: 94/05039 (1994-03-01), None
Beddingfield, C., et al., “Flip Chip Assembly of Motorola Fast Static RAM Known Good Die”,1997 Proceedings, 47th Electronic Components and Technology Conference, San Jose, CA, 643-648, (May 18-21, 1997).
Blalock, T.N., et al., “A High-Speed Clamped Bit-Line Current-Mode Sense Amplifier”,IEEE Journal of Solid-State Circuits, 26(4), 542-548, (Apr. 199

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