Silicon etch rate enhancement

Details Silicon etch rate enhancement Silicon etch rate enhancement

1987-05-04

1988-08-23

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156657, 1566591, 1566611, 156662, 20412965, 252 791, 252 795, 428138, 428450, 428620, 437228, 437246, H01L 21306, B44C 122, C03C 2506, C03C 1500

Patent

active

047658657

ABSTRACT:
This invention is directed to a method for increasing the etch rate of a single crystal silicon wafer in an anisotropic etching solution. This method comprises applying a mask material to a portion of one face of the wafer and a metal coating to substantially the entire surface of an opposite face of the wafer which renders the electrode potential of the masked, metal coated single crystal silicon wafer more anodic than that of a masked, single crystal silicon wafer alone, and exposing the coated wafer to a suitable anisotropic etching solution. This method may further comprise applying an external anodic voltage to the masked, metal coated single crystal silicon wafer, which voltage is less than that which causes the electrode potential of the masked, metal coated single crystal silicon wafer to exceed the passivation potential of the masked, single crystal silicon wafer.

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O. Glembocki et al. in "Bias-Dependent Etching of Silicon in Aqueous KOH", J. Electrochem. Soc.: Solid-State Science and Technology, Jan. 1985, vol. 132, No. 1, pp. 145-151.

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