Silicon epitaxial wafer manufacturing method

Details Silicon epitaxial wafer manufacturing method Silicon epitaxial wafer manufacturing method

1999-09-14

2001-07-17

Hiteshew, Felisa (Department: 1765)

Single-crystal, oriented-crystal, and epitaxy growth processes;

Processes of growth from liquid or supercritical state

Having pulling during growth

C117S019000

Reexamination Certificate

active

06261362

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a method of manufacturing silicon epitaxial wafers having a silicon epitaxial film vapor-grown on a prescribed surface, for use as materials for highly integrated semiconductor devices, and to improvements in a manufacturing method therefor with the object of reducing defects called light point defects (LPDs) that occur in the surface thereof.
The present invention relates to a silicon epitaxial wafer manufacturing method wherein, using a CZ method or MCZ method (hereinafter referred to as the CZ method) that utilizes the fact that, whereas the COP (Crystal-originated particles) density is high in wafers wherein the carbon content has deliberately been made high, the size thereof is small, and, when growing the epitaxial film, wafers are solution-annealed or flattened to eliminate COPs, whereby the carbon concentration in the monocrystals is controlled so that it is made deliberately high, within a prescribed range, and silicon monocrystalline ingots are grown with a comparatively high pulling speed, wherefrom selection is made so that the grown-in defect density in the wafer surface is 0.03 defects/cm
2
or lower with a size of 0.130 &mgr;m or greater, whereupon, using these selected wafers, the epitaxial film is formed, whereby the silicon epitaxial wafers grown are compatible with extremely high-quality next-generation high-integration devices.
DESCRIPTION OF THE PRIOR ART
In conventional semiconductor devices (equivalent to 4M and 16M devices), a design rule has generally been used involving a line width broader than 0.35 &mgr;m or so. It is said that the grown-in defects (COPs=crystal-originated particles) of a size ⅔ or more of this line-width size affect the actual device characteristics. This critical COP size value is sometimes deemed to be ½ by device manufacturers taking a stricter view.
Conventionally, to be more specific, although the COP size deemed to affect the devices differs somewhat depending on the device manufacturer and device application, COPs smaller than 0.233 &mgr;m (or smaller than 0.175 &mgr;m if the stricter view is taken) present on the wafer surface (such as in a density of 0.3 COPs/cm
2
of a size of 0.20 &mgr;m, for example) are not believed to have all that much effect on device characteristics or final yield, and hence have not been considered problematic.
However, with further advances toward finer design rules in next-generation highly integrated devices, the very small, low-density COPs present on the surfaces of devices previously considered non-problematic are now definitely known to have adverse effects on device characteristics, so that the reduction of these COPs is considered absolutely indispensable to obtaining good final device production yield.
Conventionally, efforts to resolve this problem in wafers considered comparable to 4M and 16M devices have been focused on improving the growth process at the time of crystal lifting. A representative example of such an improvement approach that has been employed involves pulling the crystals at a considerably slower pulling speed than was previously used. These methods have been employed wherein the pulling speed is reduced by 30% to 60%.
It is known that when wafers cut from crystals made by pulling at such low speeds are subjected to a thermal oxidation process at 1000° C. to 1150° C., a ring-shaped oxidation-inducing lamination defect called an oxidation-induced stacking fault (OSF) develops.
Furthermore, when the pulling speed is slowed down even further, the OSF ring contracts further until, ultimately, it disappears at the center of the wafer. As a result, the COP density is reduced over the entire surface of the wafer.
In other words, with the prior art, efforts to reduce COP occurrence density have focussed on slowing down the crystal pulling speed.
However, when this pulling speed is slowed down, a problem arises in that the pulling time is lengthened, whereupon the danger of dislocations developing is heightened. The development of such dislocations induces a decline in crystal pulling yield.
Another problem with crystals pulled at low speed is that productivity becomes significantly poorer than when the crystals are pulled at high speed. This results in a higher-cost manufacturing method than that of producing crystals by high-speed pulling.
It is now apparent that the design rule will be diminished to 0.25 &mgr;m in coming high-density devices (equivalent to 256M and 1G and beyond), and further diminished to 0.18 &mgr;m in the near future, whereupon it has become necessary to study COPs of an even smaller size, down to the 0.09 &mgr;m level when viewed in terms of the design rule severity discussed earlier.
However, it will be extremely difficult to achieve further COP reduction with the conventionally employed techniques, that is, with improvements involving modifications in crystal pulling conditions. As noted already, moreover, in terms of cost, the conventional low-speed pulling method is particularly problematic.
In view of what has been said, in devices having high integration levels of 256M or more, there is a strong possibility that epitaxial wafers will be used for device substrates instead of mirror-finished wafers cut from crystals produced using modified crystal pulling methods.
That is, compared with the mirror-finished wafers, in epitaxial wafers there exist few if any grown-in defects in the epitaxial layer which would cause device characteristics to deteriorate, wherefore it is possible to obtain extremely high surface quality.
To date, epitaxial wafers have not been used very extensively due to their higher cost as compared with mirror-finished wafers. Nevertheless, unless the COP problem associated with methods based on modified crystal pulling conditions can be overcome, it is believed that the epitaxial wafer will come to be the wafer of choice for highly integrated device substrates.
However, even if high-quality epitaxial wafers are adopted, there is a danger that, depending on the quality of the substrate wafer used as the base layer therefor, defects will develop, on the epitaxial surfaces grown, that will adversely affect device characteristics, thereby nullifying the expectation for the high-quality surface conditions considered the primary merit of the epitaxial wafer.
That is, in wafers cut from crystals pulled at low speed, among these COPs are some which continue to exist without flattening or disappearing even when subjected to an etching action in an atmosphere of hydrogen and hydrogen chloride during the epitaxial growth process. Hence COP-induced defects (LPDs) develop in the epitaxial layer surface.
Dislocation clusters readily develop in wafers cut from crystals pulled at low speed. Accordingly, when dislocation clusters are present on the wafer surface, even though an epitaxial growth process is performed, the dislocation clusters do not disappear, but appear just as they are on the growth surface, causing a significant decline in the epitaxial surface quality, which is a problem.
In other words, with improved methods based on the modified crystal pulling speed described earlier, problems remain in terms of productivity, cost, production yield, and surface quality perfection as represented by COPs.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a manufacturing method capable of producing high-quality epitaxial wafers at high yield, wherewith it is possible to efficiently manufacture ideal low-COP substrates for the epitaxial wafers in order to obtain, in the described epitaxial wafers, high epitaxial surface quality without adversely affecting device characteristics.
The inventors conducted various studies on wafers with the objective of efficiently manufacturing epitaxial wafers that exhibit extremely low COP generation volume in the epitaxial wafer surface and are suitable for use in manufacturing next-generation high-quality integrated devices.
As a result of these studies, the inventors learned that, in wafers made by low-speed pulling,

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