Silicon-enriched shallow trench oxide for reduced recess during

Details Silicon-enriched shallow trench oxide for reduced recess during Silicon-enriched shallow trench oxide for reduced recess during

1997-08-06

2000-01-11

Chaudhuri, Olik

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438221, H01L 2176, H01L 218238

Patent

active

060135581

ABSTRACT:
A method of isolating a semiconductor device by shallow trench isolation is provided by: (a) etching a trench into the surface of an integrated circuit; (b) depositing an oxide in the trench so that at least the upper portion of the oxide is silicon-rich; (c) providing a polysilicon gate electrode on the surface of the integrated circuit, with the gate electrode being provided substantially adjacent to the trench with a space between the trench and the gate electrode; (d) providing a spacer oxide to cover the trench oxide, the gate electrode and the space between the trench and the gate electrode, so that the spacer oxide has near-stoichiometric levels of silicon; and (e) etching the spacer oxide from the surface of the integrated circuit under conditions effective to selectively etch the spacer oxide from the upper surface of the integrated circuit and from the upper surface of the gate electrode without etching the trench oxide from the upper portion of the trench.

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