Silicon corner rounding by ion implantation for shallow...

Details Silicon corner rounding by ion implantation for shallow... Silicon corner rounding by ion implantation for shallow...

1999-12-30

2001-01-16

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

C438S412000

Reexamination Certificate

active

06174787

ABSTRACT:

BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to a method for rounding corners of silicon by employing an implantation process.
2. Description of the Related Art
Field effect transistors (FET) for semiconductor devices typically include a doped active area
10
where a channel
14
forms between a source
8
and a drain
11
of the FET as shown in
FIGS. 1A and 1B
. When a gate electrode
12
is activated under proper conditions, conduction of current between source and drain occurs through a channel
14
(shown in phantom lines) below the gate electrode
12
. Isolation regions
16
are adjacent to the active area
10
.
Sharp corners
18
at the edge of the active regions
10
formed by trenches
22
which provide a location for shallow trench isolation regions
16
can cause a low threshold voltage for the transistor. This results in the transistor being switched on at lower, undesirable voltages and or current leakage through the transistor. Corners
18
also promote gate oxide defects, which may result in voltage breakage of a gate oxide layer
24
. These parasitic leakages due to the sharp corners reduce FET performance and lead to errors in data or malfunctions in the FET.
Therefore, a need exists for a method for rounding sharp corners in an active area region. A further need exists for a method for forming the rounded corners by employing ion implantation.
SUMMARY OF THE INVENTION
A method for rounding corners of a silicon substrate, in accordance with the present invention, forming a plateau on a silicon substrate having corners at edges thereof, forming a mask on a top surface of the plateau, recessing the mask back from vertical edges of the plateau to provide horizontal exposed portions, implanting one of Fluorine and Argon dopants at the corners and on the exposed portions and oxidizing the substrate such that the corners become rounded providing a gradual transition at the edges of the plateau.
A method for rounding corners of an active area plateau for a field effect transistor includes providing a silicon substrate, the silicon having a planar surface, patterning the substrate to form trenches therein such that a plateau is formed for an active area of a transistor, the plateau including corners at edges of the plateau and at base of the plateau, recessing an etch mask back from vertical edges of the plateau to provide exposed portions, implanting one of Fluorine and Argon dopants at the corners of the plateau and at corners formed at the base of the plateau, and oxidizing the substrate such that the corners of the plateau and the corners of the base of the plateau become rounded providing a gradual transition at the edges of the plateau and at the corners of the base of the plateau.
In alternate methods, the step of forming a plateau may include the steps of providing the silicon substrate, the silicon substrate having a planar surface, patterning the mask on the surface and etching trenches into the substrate to form the plateau. The step of implanting one of Fluorine and Argon dopants at the corners may include the step of implanting the one of Fluorine and Argon dopants at a dose of between about 1×10
14
ions/cm
2
and about 1×10
16
ions/cm
2
. The step of implanting one of Fluorine and Argon dopants at the corners may include the step of implanting the one of Fluorine and Argon dopants at an energy of about 10 to 50 keV. The step of oxidizing may include the step of exposing the substrate to oxygen or steam at a temperature of between about 900 and about 1100 degrees C. The step of oxidizing may include forming an oxide layer between about 5 nm and 20 nm in thickness. The mask may be recessed back by between about 5 nm and about 10 nm.
A method for masking source and drain regions during implantation, in accordance with the present invention includes the steps of providing a silicon substrate, the silicon having a planar surface, patterning a mask on the substrate over a first region, implanting a second region in the substrate with dopants of a first type, implanting one of Fluorine and Argon into the second region, removing the mask from the first region, oxidizing the substrate such that the Fluorine and Argon promote an oxide layer to form over the second region which is thicker than the oxide layer over the first region and implanting the first region in the substrate with dopants of a second type such that dopants of the second type have an energy sufficient to penetrate the oxide layer over the first region but have insufficient energy to penetrate the oxide layer over the second region.
In other methods, the step of implanting one of Fluorine and Argon may include the step of implanting the one of Fluorine and Argon at a dose of between about 1×10
14
ions/cm
2
and about 1×10
16
ions/cm
2
. The step of implanting one of Fluorine and Argon may include the step of implanting the one of Fluorine and Argon dopants at an energy of about 10 to 50 keV. The step of oxidizing may include the step of exposing the substrate to oxygen or steam at a temperature of between about 900 and about 1100 degrees C. The first dopant type may include P dopants, and the second dopant type may include N dopants.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.


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