Semiconductor device manufacturing: process – Making regenerative-type switching device
Reexamination Certificate
2003-03-31
2004-10-12
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making regenerative-type switching device
C438S309000, C438S312000, C438S318000, C438S325000, C438S350000, C438S353000, C438S359000, C438S362000, C257S107000, C257S173000, C257S342000
Reexamination Certificate
active
06803259
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a silicon controlled rectifier, and particularly to a silicon controlled rectifier for SiGe process and a manufacturing method thereof.
2. Description of the Prior Art:
Over the past decade, the semiconductor technologies used in communications systems have been undergoing something of a forced divergence—between the high-integration capabilities of silicon-based processes and the high-performance possibilities of exotic processes like gallium arsenide (GaAs). Largely because of the inherent disparities between these processes, it even appeared that communications-oriented semiconductors might be finally approaching their practical limits in terms of both size reduction and performance improvement. For many applications, low-cost, high-volume silicon processes have been successfully used throughout the 1 to 2 GHz frequency domain, however for new RF applications that require much higher speed circuit operation, such as 30 GHz, standard silicon processes fall far short. On the other hand, compound III-V semiconductors such as GaAs, have been successfully implemented in these ranges, however at significant additional expense due to their exotic process requirements.
As a cost-driven market arena that intrinsically requires both performance and a high level of integration, the next generation of mobile wireless devices was literally dependent upon finding a cost-effective way to re-converge these capabilities into a unified semiconductor process. Many industry experts believe that the answer has now arrived in the form of Silicon Germanium (SiGe) process technologies.
Significant growth in both high-frequency wired and wireless markets has introduced new opportunities where compound semiconductors have unique advantages over bulk complementary metal oxide semiconductor (CMOS) technology. The key advantage of Silicon Germanium is that it is fundamentally a higher speed silicon process, thereby offering maximum leverage from existing silicon fabrication processes. By doping the silicon (Si) substrate with germanium (Ge), SiGe creates supercharged HBTs that can operate at 65 GHz as compared to 15-25 GHz for best-ofbreed silicon-only processes. With the rapid advancement of epitaxial-layer pseudomorphic SiGe deposition processes, epitaxial-base SiGe heterojunction bipolar transistors have been integrated with main stream advanced CMOS development for wide market acceptance, providing the advantages of SiGe technology for analog and radio frequency (RF) circuitry while maintaining the full utilization of the advanced CMOS technology base for digital logic circuitry.
FIG. 1
is a diagram showing a structure of SiGe hetero-junction bipolar transistor. It includes a silicon substrate
11
, p doped region
12
, n+ doped region
13
(buried collector), n well
14
, n+ doped region
16
(collector), shallow trench isolation layers
151
~
153
, p doped SiGe layer
171
, isolation layer
18
, n doped poly-silicon layer
172
, and contact plugs C, E and B. The junctions of the transistor are formed by the n well
14
, p doped SiGe layer
171
and n doped poly-silicon layer
172
.
SiGe hetero-junction bipolar transistor devices are replacing silicon bipolar junction devices as the primary element in all analog applications. With increased volume and growth in the applications that use SiGe hetero-junction bipolar transistors for external circuitry, ESD robustness is needed. This is especially the case in RF applications such as mobile phone use, where high-transistor speeds and high-frequency responses are needed. As the frequency responses of such devices increase, the loading effect on the transistor, which may lead to excessive noise and distortion, also increases.
FIG. 2A
is a diagram showing a conventional silicon controlled rectifier for Si process used for ESD protection, which is disclosed in IEDM 1995, p.337. It includes a silicon substrate
21
, p doped region
22
, n+ doped region
23
(buried layer), n well
24
, n+ doped region
261
, shallow trench isolation layers
251
~
254
, p+ doped regions
262
and
264
, p doped region
264
, n+ doped region
265
, poly-silicon layer
27
, and contact plugs B
1
, E
1
, E
2
and C
1
. The p doped region
262
and n well
24
form a PN junction, the n well
24
and p doped region
263
form a NP junction, and the p doped region
263
and n doped region
265
form another PN junction. The PNPN silicon controlled rectifier is thus formed by theses junctions. The n doped region
261
is coupled to a pad
301
, the p doped region
262
is coupled to a pad
302
, the n doped region
265
and p doped region
264
are commonly coupled to ground, and a resistor R is coupled between the p doped region
262
and n doped region
261
.
FIG. 2B
is a diagram showing an equivalent circuit of the silicon controlled rectifier shown in FIG.
2
A. It includes two bipolar junction transistors M
1
and M
2
, a resistor R, a resistor R
1
formed by the n well
24
, a resistor R
2
formed by the p doped region
262
, a resistor R
3
formed by the buried layer
23
, and a resistor R
4
formed by the p doped region
264
. The emitter, base and collector of the transistor M
1
are respectively coupled to the pad
301
, the resistor R
2
and ground. The emitter, base and collector of the transistor M
2
are respectively coupled to ground, the resistor R
4
and R
3
. Thus, ESD paths may be provided between the pad
301
,
302
and ground.
Theoretically, the structure in
FIG. 2A
may be applied to that shown in
FIG. 1
for a SiGe hetero-junction SCR. However, such an SCR structure has to be improved since the resistor R and the doped region
261
are necessary, which is disadvantageous to circuit size and complicates the process.
SUMMARY OF THE INVENTION
The object of the present invention is to provide an SCR for SiGe process without the additional resistor and doped region used in the conventional SCR.
The present invention provides a silicon controlled rectifier for SiGe process. The silicon controlled rectifier comprises a substrate, a buried layer of a first conductivity type in the substrate, a well of the first conductivity type in the substrate and above the buried layer, a doped region of a second conductivity type in the well, a first conducting layer of the second conductivity type on the substrate, and a second conducting layer of the first conductivity type on the first conducting layer.
The present invention further provides a method for manufacturing a silicon controlled rectifier for SiGe process. The method comprises the steps of providing a substrate, forming a buried layer of a first conductivity type in the substrate, forming a well of the first conductivity type in the substrate and above the buried layer, forming a doped region of a second conductivity type in the well, forming a first conducting layer of the second conductivity type on the substrate, and forming a second conducting layer of the first conductivity type on the first conducting layer.
The present invention further provides an integrated circuit comprising a core circuit; and an ESD protection device protecting the core circuit from ESD damages. The ESD protection device includes a substrate, a buried layer of a first conductivity type in the substrate, a well of the first conductivity type in the substrate and above the buried layer, a doped region of a second conductivity type in the well, a first conducting layer of the second conductivity type on the substrate, and a second conducting layer of the first conductivity type on the first conducting layer.
REFERENCES:
patent: 6239463 (2001-05-01), Williams et al.
patent: 6576974 (2003-06-01), Chang et al.
patent: 6586818 (2003-07-01), Voldman
patent: 2002/0153571 (2002-10-01), Mergens et al.
patent: 2003/0047750 (2003-03-01), Russ et al.
patent: 2004/0110353 (2004-06-01), Mallikarjunaswamy
S. Voldman et al., Electrostatic Discharge Characterization of Epitaxial-Base Silicon-Germanium Hetrojunction Bipolar Transisto
Keshavan B. V.
Taiwan Semiconductor Manufacturing Co. Ltd.
Thomas Kayden Horstemeyer & Risley
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