Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1997-08-01
1998-11-17
Bowers, Charles
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
438697, 438424, 438425, 438426, 438435, 438437, 438296, 438221, 438692, 148DIG50, H01L 2144, H01L 2148
Patent
active
058376127
ABSTRACT:
A method for forming shallow trench isolation (STI) (100) begins by forming an oxidizable layer (106) preferably made of polysilicon. An opening is patterned and etched through this layer (106) to define and form the trench isolation region (108). Silicon sidewalls of the trench (108) and the polysilicon layer (106) are then exposed to an oxidizing ambient to form a thermal oxide trench liner (107a) and an erosion-protection polysilicon-oxide layer (107b). A trench fill material (110a) is then deposited and chemically mechanically polished (CMP) utilizing the polysilicon layer (106) as a polish stop. The final polished trench fill plug comprises an ozone TEOS bulk material (110c) and an annular peripheral upper erosion-protection portion formed of the polysilicon-oxide (107d). The annular polysilicon-oxide protection regions (107d) either reduce or entirely eliminate adverse sidewall parasitic erosion which occurs in conventional trench technology when processing active areas (124).
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Ajuria Sergio
Kao Soolin
Bowers Charles
Larson J. Gustav
Motorola Inc.
Nguyen Thanh
Witek Keith E.
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