Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-15
2002-09-24
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S077000, C257S342000
Reexamination Certificate
active
06455892
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of Japanese Patent Application No. 11-267529 filed on Sep. 21, 1999, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to silicon carbide semiconductor devices, especially to insulation gate type field effect transistors such as a high-power vertical power MOSFET, and a method for manufacturing the same.
2. Description of the Related Art
JP-A-10-308510 discloses a planar type MOSFET shown in FIG.
7
. Referring to
FIG. 7
, the MOSFET includes an n
+
type silicon carbide (SiC) semiconductor substrate (n
+
type substrate)
1
having an upper surface as a main surface
1
a
and a lower surface as a back surface
1
b
at an opposite side of the main surface
1
a
. An n
−
type silicon carbide epitaxial layer (n
−
type epi layer)
2
having a dopant concentration lower than that of the substrate
1
is disposed on the main surface
1
a
of the substrate
1
.
Base regions formed by p
−
type silicon carbide (p
−
type base regions)
3
a
,
3
b
are provided in predetermined surface portions of the n
−
type epi layer
2
separate from each other. An n
+
type source region
4
a
is provided in a predetermined surface portion of the p
−
type base region
3
a
, which is shallower than the p
−
type base region
3
a
. An n
+
type source region
4
b
is provided in a predetermined surface portion of the p
−
type base region
3
b
, which is shallower than the p
−
type base region
3
b.
An n
−
type SiC layer
5
extends in surface portions of the n
−
type layer
2
and the p
−
type base regions
3
a
,
3
b
, between the n
+
type source regions
4
a
and
4
b
. That is, the n
−
type SiC layer
5
extends in the p type base regions
3
a
,
3
b
to connect the source regions
4
a
,
4
b
and the epi layer
2
. The n
−
type SiC layer
5
is an epitaxial layer formed through epitaxial growth and having a crystal structure of
4
H,
6
H, or
3
C. The epitaxial layer can have a specific crystal structure regardless of the crystal structure of the underlying substrate. The n
−
type SiC layer
5
works as a channel layer at a surface of a device when the device is operated, and therefore, hereinafter it is referred to as a surface channel layer
5
.
The dopant concentration of the surface channel layer
5
is in a range of 1×10
15
cm
−3
to 1×10
17
cm
−3
, which is generally lower than those of the n
−
type epi layer
2
and the p
−
type base regions
3
a
,
3
b
, thereby lessening the on-resistance.
A gate insulating film (silicon oxide film)
7
is formed on the upper surfaces of the surface channel layer
5
and the n
+
type source regions
4
a
,
4
b
, and a gate electrode
8
is formed on the gate insulating film
7
. The gate electrode
8
is covered with an insulating film
9
composed of an LTO (Low Temperature Oxide) film. A source electrode
10
is formed on the insulating film
9
and contacts the n
+
type source regions
4
a
,
4
b
and the p
−
type base region
3
a
,
3
b
. A drain electrode
11
is formed. on the back surface
1
b
of the substrate
1
.
The semiconductor device described above can operate as an accumulation mode device without forming an inversion layer. Therefore, the channel mobility can be increased and the on-resistance can be reduced in comparison to an inversion mode MOSFET requiring an inversion layer. Thus, the accumulation mode MOSFET can reduce the on-resistance; however, there is a need to further decrease the on-resistance.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above limitation. An object of the present invention is to reduce an on-resistance of an accumulation mode MOSFET.
An on-resistance of a MOS structure includes a channel resistance that is determined by a channel mobility and a carrier concentration of a channel region. The carrier concentration is determined by a doping concentration of an accumulation channel portion and a gate voltage. The channel mobility is determined by crystallinity of the channel region, and the like. Factors for increasing the on-resistance have been studied in view of the channel mobility.
In the conventional MOSFET, the channel region is formed in the surface portion of the surface channel layer
5
, specifically at the interface between the surface channel layer
5
and the gate insulating film
7
. The channel mobility is therefore affected by the interface state even in the accumulation mode MOSFET. It is assumed that the channel mobility is reduced due to roughness or defects produced by residue carbon at the MOS interface so that the on-resistance is increased.
Therefore, to achieve the above object, a silicon carbide semiconductor device according to the present invention has a surface channel layer that is composed of a first channel layer of a first conductivity type contacting a base region and a semiconductor layer, and a second channel layer of a second conductivity type disposed on the first channel layer. A gate insulating film is disposed on the second channel layer.
In this MOSFET, when an electric potential of a gate electrode is approximately zero, the surface channel layer can be set at a pinch-off state by a depletion layer extending from the second channel layer and a depletion layer extending from the base region. A channel can be formed in the first channel layer underlying the second channel layer without being affected by a state of an interface (MOS interface) between the surface channel layer and the gate insulating film. As a result, the channel mobility is improved and the on-resistance is reduced sufficiently.
The second channel layer should have a carrier concentration and a thickness that are determined such that the channel is formed in the first channel layer before a triangle potential is formed at the interface between the second channel layer and the gate insulating film. The second channel layer can be formed by ion-implanting second conductivity type impurities into the first channel layer or by epitaxial growth.
REFERENCES:
patent: 4800415 (1989-01-01), Simmons et al.
patent: 5712501 (1998-01-01), Davies et al.
patent: 5977564 (1999-11-01), Kobayashi et al.
patent: 6097063 (2000-08-01), Fujihara
patent: 10-308510 (1998-11-01), None
S. Wolf and R. N. Tauber, “Silicon Processing for the VLSI Era”, vol. 3—The Submicron MOSFET, Lattice Press, Sunset Beach, California; p. 136-138 (“4.1.1 Basics of MOSFET Operation”), 1995 (ISBN 0-961672-5-3).*
Frank Stern, “Self-Consistent Results for n-Type Si Inversion Layers”, The Physical Review B, vol. 5, No. 12, pp. 4891-9 (Jun., 1972).*
T. Ando, A.B. Fowler and F. Stern, “Electronic Properties of Two-Dimensional Systems”, in Reviews of Modern Physics, vol. 54, pp. 437-672 (1982).*
U.S. patent application Ser. No. 09/265,582, Miyajima, filed May 10, 1999.
Amano Shinji
Okuno Eiichi
Denso Corporation
Flynn Nathan J.
Law Offices of David G. Posz
Mondt Johannes
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