Silicon carbide semiconductor device

Details Silicon carbide semiconductor device Silicon carbide semiconductor device

2000-07-26

2002-09-17

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S330000, C257S332000, C257S742000, C257S743000, C257S744000

Reexamination Certificate

active

06452228

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a silicon carbide semiconductor device, especially to an insulated gate type field effect transistor such as a high-power vertical MOSFET, and a method of manufacturing the same.
2. Description of the Related Art
The applicant of the present invention proposes in pending U.S. patent application Ser. No. 09/035,204 a planar-type MOSFET for improving channel mobility and for lowering ON-resistance. Referring to
FIG. 1
, the planar-type MOSFET includes an n
+
type semiconductor substrate
1
made of silicon carbide (SiC) and having a main surface
1
a
and a back surface
1
b
on a side opposite to the main surface
1
a
. An n
−
type epitaxial layer (herebelow, referred to as n
−
epi-layer)
2
is formed on the main surface
1
a
of the n
+
type semiconductor substrate
1
to have a dopant (impurity) concentration lower than that of the substrate
1
. In specific surface regions of the n
−
type epi-layer
2
, p
−
type base regions
3
a
,
3
b
are formed at a specific depth to be separated from one another. In specific surface regions of the p
−
type base regions
3
a
,
3
b
, n
+
type source regions
4
a
,
4
b
are formed at a depth shallower than that of the base regions
3
a
,
3
b.
An n
−
type SiC layer
5
is extended in surface regions of the n
−
type epi-layer
2
and the p
−
type base regions
3
a
,
3
b
, between the n
+
type source regions
4
a
,
4
b
, thereby connecting the source regions
4
a
,
4
b
and the n
−
type epi-layer
2
via the surface regions of the p
−
type base regions
3
a
,
3
b
. The n
−
type SiC layer
5
is formed through epitaxial growth to have 4H, 6H, or 3C type crystal structure. When the device is operated, the n
−
type SiC layer
5
functions as a channel formation layer. Herebelow, the n
−
type SiC layer
5
is referred to as a surface channel layer. The surface channel layer
5
is doped with nitrogen (N) as dopant, with a low dopant concentration, for example, in a range of 1×10
15
cm
−3
to 1×10
17
cm
−3
which is generally less than the dopant concentrations of the n
−
type epi-layer
2
and the p
−
type base regions
3
a
,
3
b
. Accordingly, low ON-resistance is realized.
A gate oxide film
7
is formed from silicon dioxide (SiO
2
) on the surface channel layer
5
and the n
+
type source regions
4
a
,
4
b
, and a gate electrode
8
is further formed on the gate oxide film
7
. The gate electrode
8
is covered with an insulation film
9
. The insulation film
9
is made of LTO (Low Temperature oxide). A source electrode
10
is formed on the insulation film
9
to contact the n
+
type source regions
4
a
,
4
b
and p
−
type base regions
3
a
,
3
b
. A drain electrode layer
11
is formed on the back surface
1
b
of the n
+
type semiconductor substrate
1
.
The thus constructed planar-type MOSFET operates at an accumulation mode in which a channel region is induced without inverting the conductive type of the channel formation layer. Therefore, the channel mobility can be increased and the ON-resistance can be lowered as compared with those of an inversion mode MOSFET which is accompanied by inversion of the conductive type to form a channel.
The inventors of the present invention manufactured the planar-type power MOSFET described above, and examined the gate oxide film
7
of the MOSFET by means of light illumination C-V measurement. The resultant C-V characteristic is shown in FIG.
2
. As a result, it was founded that the C-V characteristic was largely varied by illumination, and after that it did not recover immediately. That is, it was founded that the C-V characteristic had the so-called hysteresis characteristic. In addition, a flat-band voltage was shifted to a positive side. This implies that electron traps arose.
This phenomenon indicates that carrier traps exist in the gate oxide film or at an interface between the gate oxide film and the surface channel layer
5
(SiO
2
/SiC interface), and can cause not only instability of FET characteristics but deterioration in reliability to the gate oxide film
7
.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above problem. An object of the present invention is to provide a MOSFET having stable FET characteristics and high reliability to a gate insulation film thereof.
The inventors of the present invention have studied concerning the problem described above, and found that Si—N bonds existed at the SiO
2
/SiC interface as a result of XPS measurement setting detector angle ⊖ to 5° as shown in FIG.
3
. That is, nitrogen used as dopant for the surface channel layer
5
shown in
FIG. 1
reacts with silicon carbide during a thermal oxidation treatment for forming the gate oxide film
7
so as to produce silicon nitride (SiN) which can cause carrier (electron or hole) traps.
Therefore, according to a first aspect of the present invention, a surface channel layer includes nitrogen with a concentration of equal to or less than 1×10
15
cm
−3
. Accordingly, an amount of silicon nitride existing in a gate insulation film and at an interface between the surface channel layer and the gate insulation film becomes so extremely small that the carrier trap concentration is negligibly small, resulting in stable FET characteristics and improved reliability to the gate insulation film.
According to a second aspect of the present invention, the surface channel layer includes an element as dopant selected from the fifteenth group elements other than nitrogen in the periodic table. In this case, the concentration of the dopant in the surface channel layer is in a range of 1×10
15
cm
−3
to 1×10
17
cm
−3
. The concentration of the unintendedly doped nitrogen should be equal to or less than 1×10
15
cm
−3
. As a result, the amount of silicon nitride existing in the gate insulation film and at the interface between the surface channel layer and the gate insulation film becomes so extremely small that the carrier trap concentration is negligibly small.
Preferably, an interface state density at the interface between the gate insulation film and the surface channel layer is controlled to be equal to or less than 4×10
11
cm
−2
eV
−1
. Accordingly, the stability of the FET characteristics is further improved without increasing ON resistance.
According to a third aspect of the present invention, after the gate insulation film is formed, a high temperature annealing treatment is carried out at a temperature equal to or higher than 1200° C. Si—N bonds capable of causing carrier traps are decomposed during the high temperature annealing treatment. The high temperature annealing treatment is preferably performed in ambience including at least one of hydrogen, oxygen and an inert gas. Consequently, even when the concentration of nitrogen in the surface channel layer is larger than 1×10
15
cm
−3
, the amount of silicon nitride is sufficiently reduced, resulting in stable FET characteristics and improved reliability to the gate insulation film.
According to a fourth aspect of the present invention, after the gate oxide film is formed by thermally oxidizing a surface portion of the surface channel layer at a first temperature, a reoxidation treatment is performed in oxidation ambience at a second temperature lower than the first temperature. Further, annealing is performed at an oxidation rate smaller than that in the reoxidation treatment.
In this case, Si—N bonds taken into the gate insulation film during the reoxidation treatment performed at a large oxidation rate can be decomposed by reacting with oxygen during the annealing performed at an extremely small oxidation rate. As a result, the carrier traps caused by Si—N bonds are reduced, resulting in stable FET characteristics and improved reliability to the gate insulation film. The o

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