Silicon based vertical tunneling memory cell

Details Silicon based vertical tunneling memory cell Silicon based vertical tunneling memory cell

2000-06-09

2002-09-10

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Diffusing a dopant

C438S200000, C438S237000, C438S979000

Reexamination Certificate

active

06448161

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to the design of memory cells and, more particularly, to a memory cell consisting of a metal oxide silicon (MOS) transistor structure and a resonant tunneling diode (RTD) device.
BACKGROUND OF THE INVENTION
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down device dimensions at submicron levels on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. High density random access memory (RAM) devices have reached the gigabyte level with the introduction of the dynamic RAM (DRAM). The DRAM memory cell can consist of a single pass transistor and a capacitor to obtain the smallest possible cell size. However, DRAM devices require periodic refreshing, typically in the order of once per millisecond, since a bit stored as a charge on a capacitor leaks away at a fairly fast rate. Static RAM (SRAM) devices provide enhanced functionality since no refreshing is need and are also generally faster than a DRAM device. However in general the SRAM device is more complex, requiring either six transistors or four transistors and two load resistors. It is therefore desirable to have memory cells with functional qualities of SRAM devices but with cell sizes closer to the DRAM devices.
A memory cell using a negative differential resistance elements has drawn much attention as a memory structure able to form an SRAM with a more simplified structure. If a load is connected to a differential resistance element, three stable operating points can be obtained. An SRAM cell can be formed by employing two of the three stable operating points. A resonant tunneling diode (RTD) latch typically consists of a sequence of five semiconductor layers. The outer two layers are contact layers and the inner three layers include two narrow tunneling barrier layers and a middle wide layer referred to as a quantum well. Each layer differs in their respective energy bandwidths necessary to tunnel through the RTD and provide current flow. The sequence of layers produces an energy profile through which electrons travel and can include two energy barriers (e.g., the tunneling barriers) separate by a narrow region (e.g., the quantum well). Typically, an electron with energy referred to as the Fermi energy, approaching the first tunneling barrier is reflected. However, as the dimensions of the tunneling barrier decrease toward the wavelength of the electron, the electron begins tunneling through the barrier causing current to flow. Since RTD structures have positive qualities such as high speed, high noise immunity, low power and can be fabricated at high densities, the structure becomes ideally suited for memory devices. However, improvements in fabrication and size are always highly desirable.
In view of the above, it is apparent that there is a need in the art for a method of providing an SRAM memory device that is smaller and consumes less power than conventional SRAM memory devices. It is also apparent that improved methods of fabricating such devices are also needed.
SUMMARY OF THE INVENTION
The present invention provides for a method of forming an SRAM memory device from a single transistor and a single RTD structure. One aspect of the invention relates to a method of forming a memory device. The method comprises the steps of forming a silicon base, an oxide layer over the base and a top thin silicon layer over the oxide layer. The top silicon layer has a first region and a second region. The second region is masked and a transistor device is formed in the first region of the top silicon layer. Next, the first region is masked and a vertical RTD device is formed in the second region. The step of forming a vertical RTD device in the second region comprises implanting a n
+
dopant to form concurrently a source and drain region of the transistor device and a generally horizontal N
+
quantum well region of the vertical RTD device. The drain region of the transistor device is coupled to the quantum well region of the vertical RTD. The N
+
quantum well region is disposed horizontally below a top surface of the second region.
Another aspect of the invention relates to a method of forming a memory device. The method comprises the steps of forming a silicon base, an oxide layer over the base and a top silicon layer over the oxide layer. The top silicon layer has a first region and a second region. The second region is masked and a gate and a P
−
body region is formed in the first region. A nitride layer is then formed over the top silicon layer. A spacer pair is formed adjacent opposite sides of the gate by etching away the nitride layer. N
+
source and N
+
drain regions are formed in the first region and a N
+
quantum well region in the second region of the top silicon layer. The drain region of the transistor device is coupled to the quantum well region of the vertical RTD. The N
+
quantum well region is disposed horizontally below a top surface of the second region. A first insulating layer is deposited over the top surface of the silicon layer. The first insulating layer is then removed from the first region forming a resistor protection mask over the second region. A first silicide is deposited over the gate and the N
+
source and N
+
drain regions.
A second insulating layer is then deposited over the top surface of the silicon layer. A second nitride layer is deposited over the second insulating layer. A first opening is formed above the N
+
quantum well region on a first end of the N
+
quantum well region and a second opening is formed above the N
+
quantum well region on a second end of the N
+
quantum well region. A first thin layer of undoped silicon is then deposited in the first opening to form a first tunneling barrier and a second thin layer of undoped silicon is deposited in the second opening to form a second tunneling barrier. An in-situ P
+
amorphous layer is deposited over the first and second regions and the RTD structure is polished to remove a predetermined thickness of the amorphous layer equivalent to the thickness of the amorphous layer overlying the nitride layer to form a first contact region over the layer of undoped silicon in the first opening and a second contact region over the layer of undoped silicon in the second opening. A second silicide is then deposited over the first contact region and the second contact region.
In yet another aspect of the invention a memory device is provided. The memory device comprises a silicon substrate, an insulating oxide layer formed over the substrate and a top silicon layer formed over the insulating oxide layer. The top silicon layer has a transistor region and a RTD structure region. A gate is formed over a region of the transistor region and a gate oxide is formed between the gate and the transistor region. An N
+
source region is formed in the transistor region and a common N
+
drain region formed in the transistor region and N
+
quantum well region formed in the RTD structure region. A first silicide is formed over the gate and the N
+
source and the N
+
drain regions. A first opening is formed above the N
+
quantum well region on a first end of the N
+
quantum well region and a second opening formed above the N
+
quantum well region on a second end of the N
+
quantum well region. A first thin layer of undoped silicon is formed in the first opening to form a first tunneling barrier and a second thin layer of undoped silicon is formed in the second opening to form a second tunneling barrier. An in-situ P
+
amorphous material is formed over the first and second openings to form a first contact region over the layer of undoped silicon in the first opening and a second contact region over the layer of undoped silicon in the second opening. A secon

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