Silicon based lateral tunneling memory cell

Details Silicon based lateral tunneling memory cell Silicon based lateral tunneling memory cell

2000-06-09

2001-09-25

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S237000, C438S979000

Reexamination Certificate

active

06294412

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to the design of memory cells and, more particularly, to a memory cell consisting of a metal oxide silicon (MOS) transistor structure and a resonant tunneling diode (RTD) device.
BACKGROUND OF THE INVENTION
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down device dimensions at submicron levels on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. High density random access memory (RAM) devices have reached the gigabyte level with the introduction of the dynamic RAM (DRAM). The DRAM memory cell can consist of a single pass transistor and a capacitor to obtain the smallest possible cell size. However, DRAM devices require periodic refreshing, typically in the order of once per millisecond, since a bit stored as a charge on a capacitor leaks away at a fairly fast rate. Static RAM (SRAM) devices provide enhanced functionality since no refreshing is need and are also generally faster than a DRAM device. However in general the SRAM device is more complex, requiring either six transistors or four transistors and two load resistors. It is therefore desirable to have memory cells with functional qualities of SRAM devices but with cell sizes closer to the DRAM devices.
A memory cell using a negative differential resistance elements has drawn much attention as a memory structure able to form an SRAM with a more simplified structure. If a load is connected to a differential resistance element, three stable operating points can be obtained. An SRAM cell can be formed by employing two of the three stable operating points. A resonant tunneling diode (RTD) latch typically consists of a sequence of five semiconductor layers. The outer two layers are contact layers and the inner three layers include two narrow tunneling barrier layers and a middle wide layer referred to as a quantum well. Each layer differs in their respective energy bandwidths necessary to tunnel through the RTD and provide current flow. The sequence of layers produces an energy profile through which electrons travel and can include two energy barriers (e.g., the tunneling barriers) separate by a narrow region (e.g., the quantum well). Typically, an electron with energy referred to as the Fermi energy, approaching the first tunneling barrier is reflected. However, as the dimensions of the tunneling barrier decrease toward the wavelength of the electron, the electron begins tunneling through the barrier causing current to flow. Since RTD structures have positive qualities such as high speed, high noise immunity, low power and can be fabricated at high densities, the structure becomes ideally suited for memory devices. However, improvements in fabrication and size are always highly desirable.
In view of the above, it is apparent that there is a need in the art for a method of providing an SRAM memory device that is smaller and consumes less power than conventional SRAM memory devices. It is also apparent that improved methods of fabricating such devices are also needed.
SUMMARY OF THE INVENTION
The present invention provides for an SRAM memory cell device comprised of a single transistor and a single RTD latch structure. The single transistor and RTD latch structure are formed on a very thin silicon layer, typically in the range of 250 to 300 Å thick, allowing for increased memory cell density over a given area. The RTD latch structure is a lateral RTD device, such that the outer contacting regions, the tunneling barriers and the central quantum well are formed side-by-side as opposed to being stacked on top of one another. This allows for formation of the memory cell device on very thin silicon layers. The layers can then be stacked to form memory devices for use with computers and the like. The memory device can be formed employing silicon-on-insulator (SOI) technology to take advantage of SOI device characteristics.
One aspect of the invention relates to a method of forming a memory device. The method comprises the steps of forming a silicon base, an oxide layer over the base and a top thin silicon layer over the oxide layer. The top silicon layer has a first region and a second region. The second region of the top thin silicon layer is masked and a transistor device is formed in the first region of the top thin silicon layer. The first region of the top thin silicon layer is then masked and a lateral RTD device is formed in the second region of the top thin silicon layer.
Another aspect of the invention relates to a method of forming a memory device, comprising the steps of forming a silicon base, an oxide layer over the base and a top thin silicon layer over the oxide layer. The top silicon layer has a first region and a second region. The second region of the top silicon layer is masked and a gate and a P
−
body region are formed in the first region. A nitride layer is then formed over the top silicon layer. A region of the nitride layer is masked over a central region of the second region. A first spacer pair is then formed adjacent opposite sides of the gate and a nitride dummy mask are formed over the central region of the second region. N
+
source and N
+
drain regions are formed in the first region of the top silicon layer. A second spacer pair is formed adjacent opposite sides of the nitride dummy mask in the second region. P
+
outer contact regions are formed in the second region of the top silicon layer. A plasma oxide layer is then deposited over the second region of the top silicon layer and the nitride dummy mask is removed from the central region of the second region. A N
+
central region or quantum well is formed in the second region of the top silicon layer, such that undoped tunneling barriers remain below each of the second pair of spacers between the central region and the P
+
outer contact regions. An oxide layer is then deposited over the top silicon layer and contacts are formed to the gate, the N
+
drain region and the P
+
outer contact regions.
Yet another aspect of the invention relates to a memory device. The memory device comprises a silicon base, an oxide layer over the base and a top thin silicon layer over the oxide layer. The top silicon layer has a first region and a second region. A transistor structure is disposed in the first region and a laterally displaced RTD structure is disposed in the second region wherein a drain region of the transistor structure is coupled to a central region of the RTD structure.
Another aspect of the invention relates to an SOI NMOS memory device. The memory comprises a silicon substrate, an insulating oxide layer formed over the substrate and a top silicon layer formed over the insulating oxide layer. The top silicon layer has a transistor region and a RTD structure region. A gate is formed over a region of the transistor region and a gate oxide is formed between the gate and the transistor region. N
+
source and N
+
drain regions are formed in the transistor region. A N
+
central region is formed in the RTD structure region coupled to the N
+
drain region. Undoped silicon regions are formed on opposite sides of the N
+
central region and P
+
outer contact regions are formed on sides of the undoped silicon region opposite the N
+
central region.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the in

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