Silicon backside etch for semiconductors

Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step

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156630, 156653, 156657, 156662, 252 795, 357 2311, 437 52, 437225, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

050644980

ABSTRACT:
A technique for analyzing defective semiconductor chips is disclosed. The silicon substrate of the chip is etched away, leaving the memory cells exposed for viewing. The method includes the steps of: removing oxide from the backside of a semiconductor device; and, placing the semiconductor device into a solution of choline and water. The solution etches away the substrate. The memory cells may be photographed and viewed by TEM and SEM techniques.

REFERENCES:
patent: 3721588 (1973-03-01), Hays
patent: 3923567 (1975-12-01), Lawrence
patent: 4544416 (1985-10-01), Meador et al.
patent: 4924589 (1990-05-01), Leedy
patent: 4978634 (1990-12-01), Shen et al.
Reinhard Lemme et al., "Failure Analysis of DRAMs", Siemens AG, Munich, FRG, pp. 31-39.

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