Silicon annealed wafer and silicon epitaxial wafer

Details Silicon annealed wafer and silicon epitaxial wafer Silicon annealed wafer and silicon epitaxial wafer

2007-09-25

2007-09-25

McNeil, Jennifer (Department: 1775)

Stock material or miscellaneous articles

Circular sheet or circular blank

C428S446000, C117S928000, C423S348000

Reexamination Certificate

active

10809712

ABSTRACT:
A silicon annealed wafer having a sufficient thick layer free from COP defects on the surface, and a sufficient uniform BMD density in the inside can be produced by annealing either a base material wafer having nitrogen at a concentration of less than 1×1014atoms/cm3, COP defects having a size of 0.1 μm or less in the highest frequency of occurrence and no COP defects having a size of 0.2 μm or more, oxygen precipitates at a density of 1×104counts/cm2or more, and BMDs (oxygen precipitates), where the ratio of the maximum to the minimum of the BMD density in the radial direction of the wafer is 3 or less, or a base material wafer grown at specific average temperature gradients within specific temperature ranges and specific cooling times for a single crystal at a nitrogen concentration of less than 1×1014atoms/cm3, employing the Czochralski method. Moreover, a silicon epitaxial wafer having very small defects and a uniform BMD distribution in the inside can be formed by growing an epitaxial layer on the surface of either the first type base material wafer or the second type base material wafer. Both the silicon annealed wafer and the silicon epitaxial wafer greatly reduce the rate of producing defective devices, thereby enabling the device productivity to be enhanced.

REFERENCES:
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patent: 6413310 (2002-07-01), Tamatsuka et al.
patent: 6573159 (2003-06-01), Kobayashi et al.
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patent: 11-189493 (1999-07-01), None
patent: 2001-199795 (2001-07-01), None
patent: 2002-187794 (2002-07-01), None

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