Silicide-silicon contacts for reduction of MOSFET...

Details Silicide-silicon contacts for reduction of MOSFET... Silicide-silicon contacts for reduction of MOSFET...

2002-05-15

2004-09-07

Gurley, Lynne A. (Department: 2812)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S520000, C438S523000, C438S528000, C438S533000, C438S630000, C438S649000, C438S650000, C438S651000, C438S655000, C438S659000, C438S664000, C438S682000, C438S683000

Reexamination Certificate

active

06787436

ABSTRACT:

TECHNICAL FIELD
This invention relates to MOSFETs with silicide contacts.
BACKGROUND
As VLSI devices continue to scale into the deep submicron region, interconnection delays limit circuit performance. Aluminum or polysilicon interconnections, because of their relatively slow conduction speed, exacerbate this problem. Because silicide conducts better than aluminum or silicon, the use of silicide interconnections has become widespread. Silicides are formed by combining silicon with a refractory metal, typically Ti, Co, or W. In addition to lowering the sheet resistance and forming ohmic contacts, suicides also offer high temperature thermal stability.
Despite the advantages offered by the suicides, certain disadvantages remain. For example,
FIG. 1
illustrates a portion of a typical MOSFET
5
formed using a salicide process. A silicide region
10
lies above a doped source/drain region
12
. To connect MOSFET
5
to other transistors in a circuit, a metal contact
14
also contacts silicide
10
. Accordingly, between metal contact
14
and doped source/drain region
12
, there are two intermaterial interfaces. A first intermaterial interface
16
lies between metal contact
14
and silicide
10
. The second intermaterial interface
18
lies between silicide
10
and doped source/drain region
12
. Both these interfaces will have a “contact resistance” that is a consequence of the barrier that dissimilar materials in contact have.
FIG. 2
is a band diagram for silicide/doped silicon intermaterial interface
18
. The valence and conduction bands for the silicide overlap as it is assumed to be fully metallic in character. However, the conduction and valence bands are separated in the doped silicon at the contact region illustrating the contact barrier at the interface. The contact resistances from this intermaterial interface leads to a loss of signal resulting in lower performance of the MOSFET device. Although a portion of the signal loss stems from the sheet resistivity (&rgr;) of the doped source drain region and the silicide region, the number of squares in a typical MOSFET is very low such that the contribution of resistance from these areas is relatively small. Similarly, the contact barrier from silicide/metal intermaterial interface
16
is small because silicides are metallic and metal/metal contact barriers are small. Thus, the contact barrier from silicide/doped silicon intermaterial interface emerges as the predominant contributor to the losses.
Accordingly, there is a need in the art for improved silicon silicide interfaces which minimize the loss encountered.
SUMMARY
In accordance with one aspect of the invention, a silicide layer and a doped silicon region form an interface. Either a damage-only species or a heavy metal is implanted through the silicide layer into the doped silicon region immediately adjacent the interface. The implanted species introduce traps or induce states in the bandgap of the doped silicon immediately adjacent the interface to reduce the contact barrier.
In accordance with a second aspect of the invention, a second metal is added to a refractory metal before formation of a silicide layer on a doped silicon region. After annealing the refractory metal and the doped silicon region, the second metal diffuses into the doped silicion region immediately adjacent the silicide/doped silicon interface without forming additional phases in the silicide. The diffused second metal introduces traps or induces states in the bandgap of the doped silicon immediately adjacent the interface to reduce the contact barrier.


REFERENCES:
patent: 4835112 (1989-05-01), Pfiester et al.
patent: 5624867 (1997-04-01), Cheng et al.
patent: 5858867 (1999-01-01), Hsia et al.
patent: 5933741 (1999-08-01), Tseng
patent: 6372566 (2002-04-01), Kittl et al.
patent: 6544872 (2003-04-01), Buynoski et al.
patent: 2002/0061639 (2002-05-01), Itonaga

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