Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1999-03-29
2000-08-15
Booth, Richard
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438239, 438241, 438656, 438682, 438683, H01L 218242, H01L 2144
Patent
active
061036226
ABSTRACT:
A method is disclosed for fabricating mixed analog/digital devices without incurring detrimental effects of high temperature forming of analog components such as capacitor and resistor on the silicide contacts of digital devices. Conversely, the possible adverse effects of silicide formation on the analog components is circumvented. These are accomplished by performing the silicidation of the FET device after forming the two electrode plates of the dual layer capacitor while protecting the capacitor with a capacitor protective oxide (CPO). In a second embodiment, local polysilicon (poly-Si) interconnect is formed simultaneously with the formation of the second plate of the capacitor, and the local interconnect is silicidated subsequently and simultaneously with the silicidation of the polysilicon gate and areas above the source/drain regions. In still another third embodiment, a high-value resistor is formed simultaneously with the forming of the second polysilicon electrode of the capacitor. The resistor is protected along with the capacitor by means of the CPO while the FET device area is silicidated.
REFERENCES:
patent: 5010032 (1991-04-01), Tang et al.
patent: 5604145 (1997-02-01), Hashizume et al.
patent: 5614111 (1997-03-01), Lavene
patent: 5631188 (1997-05-01), Chang et al.
patent: 5924011 (2000-03-01), Huang
patent: 6033950 (2000-03-01), Chen et al.
S. Wolf et al, "Silicon Processing for the VLSI Era", vol. 1 Lattice Press, Sunset Beach, CA, 1986, p. 386.544.
S. Wolf et al, "Silicon Processing for the VLSI Era" vol. 2, Lattice Press, Sunset Beach, CA, 1990, p. 384.
Ackerman Stephen B.
Booth Richard
Pompey Ron
Saile George O.
Taiwan Semiconductor Manufacturing
LandOfFree
Silicide process for mixed mode product with dual layer capacito does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Silicide process for mixed mode product with dual layer capacito, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicide process for mixed mode product with dual layer capacito will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2006343