Silicide gate transistors and method of manufacture

Details Silicide gate transistors and method of manufacture Silicide gate transistors and method of manufacture

2006-05-04

2009-12-15

Smith, Bradley K (Department: 2894)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE21619

Reexamination Certificate

active

07633127

ABSTRACT:
A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferably Si, SiGe, or SiGeC on a buried insulator. Raised S/D regions are formed by selective epitaxy between spacers and isolation regions. The gate is protected with a mask while the raised S/D regions are covered with a first metal layer. A first anneal affords fully silicided S/D regions. A dielectric stack is deposited on the substrate and planarized to be coplanar with the top of the spacers. The mask is removed and a second metal layer is deposited. A second anneal yields a fully silicided gate electrode. The invention is also an SOI transistor with silicided raised S/D regions and a fully silicided and optionally recessed gate.

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Tavel, B., et al., “Totally Silicided Polysilicon: A Novel Approach to Very Low-Resistive Gate Without Metal CMP Nor Etching”, International Electron Device Meeting (IEDM), Washington, DC, 2001, pp. 825-828.

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