Silicide encapsulation of polysilicon gate and interconnect

Details Silicide encapsulation of polysilicon gate and interconnect Silicide encapsulation of polysilicon gate and interconnect

1997-12-22

2001-04-17

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S199000, C438S299000, C438S303000, C438S592000, C438S595000, C438S655000, C438S656000, C438S664000

Reexamination Certificate

active

06218276

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the use of silicidation to reduce device resistance and signal propagation delays in semiconductor devices. More particularly, the present invention relates to silicide encapsulation of MOS transistor gates and interconnects.
Silicides, such as tungsten silicide (WSi
2
), titanium silicide (TiSi
2
), and cobalt silicide (CoSi
2
) are used in the semiconductor industry to enhance signal propagation through MOS transistors and other conductive features of semiconductor devices. A conventional silicide process produces a silicide region on the top of an MOS transistor's polysilicon (“poly”) gate electrode and interconnect. The silicide has a lower resistance than the underlying doped silicon or poly. As a result, signal propagation through the transistor (gate and interconnect) is enhanced.
FIGS. 1A through 1E
illustrate a conventional silicide process on a portion of a semiconductor wafer, such as is also described in S. Wolf, et al.,
Silicon Processing for the VLSI Era,
vol.1, 397-399 (Lattice Press, 1986), which is incorporated by reference herein for all purposes. In
FIG. 1A
, a portion of a semiconductor wafer
100
having a semiconductor substrate
101
(typically monocrystalline silicon) is shown. The substrate
101
has gate oxide
102
and poly
104
layers generated successively on its upper surface
106
. The gate oxide
102
and poly
104
layers are created in ways well known to those of skill in the art. For example, the gate oxide may be silicon dioxide (SiO
2
) generated by thermal oxidation of surface
106
of the silicon substrate
101
, and the poly
104
may be deposited on the gate oxide
102
by chemical vapor deposition.
FIG. 1B
shows the wafer
100
after the poly layer
104
has been patterned and etched to form a gate electrode
108
according to methods well known in the art (e.g., photolithography and plasma etching).
At this point, an ion implantation may be performed to form at least a portion of the source and drain regions. This implant is sometimes referred to as a lightly doped drain (LDD) implant and is self-aligned with polysilicon gate electrode
108
.
Next, as shown in
FIG. 1C
, a layer of dielectric
110
is deposited on the wafer surface, covering both the gate oxide
102
and the gate electrode
108
. The wafer is then subjected to an anisotropic etch which removes the dielectric
110
and gate oxide
102
on all exposed horizontal surfaces. The remaining dielectric
110
provides vertical spacers
112
. It should be noted that the terms “horizontal” and “vertical” are used herein relatively and with reference to a major surface of a semiconductor wafer, and may be interchanged. The spacers
112
act as an ion implantation mask for subsequent ion implant procedures which are used to dope portions of the substrate
101
adjacent to the gate electrode
108
in order to create or complete (depending on whether an LDD implant was performed) source
114
and drain
116
regions, as shown in FIG.
1
D. The spacers
112
, together with the remaining gate oxide
102
, separate the poly gate
108
from the source
114
and drain
116
regions. As shown in
FIG. 1E
, after ion implantation, a refractory metal, such as titanium (Ti) is deposited on the wafer surface, and silicide layers
120
,
122
and
124
are formed on the poly gate
108
, source
114
, and drain
116
regions, respectively, by reaction with the underlying poly/silicon by an alloy step well known in the art. Then, unreacted Ti is removed by a selective wet etch process, also well known in the art.
The conventional process of
FIGS. 1A-1E
results in the formation of silicide on the top surface but not the sidewalls of gate electrode. This is because sidewall spacers
112
protect the gate electrode sidewalls during silicide formation. This has the benefit of preventing the silicide layer from shorting the gate electrode to the source and drain regions. However, it has the disadvantage of providing only limited reductions in resistance. Until now, most processes did not require additional reductions in resistance. However, deep sub-micron device sizes require more significant reductions in resistance.
In order to achieve further reductions in resistance, it has been proposed that the silicide layer extend down the sidewalls of the gate electrode. U.S. Pat. Nos. 5,227,320 and 5,306,951 present examples of such silicide “encapsulated” gate electrodes. To prevent shorting between the sidewall silicide and the source drain region, these designs allow the gate oxide to extend over the source and drain regions. Unfortunately, this precludes silicide formation on the source and drain regions.
As semiconductor device feature size is scaled below 0.25 &mgr;m, interconnect and gate delays becomes increasingly important.
Accordingly, processes and apparatuses for further reducing device resistance and signal propagation delays are needed.
SUMMARY OF THE INVENTION
To achieve the foregoing, the present invention provides methods of forming a silicide layer on the exposed horizontal and vertical surfaces of a polysilicon gate electrode/interconnect in a MOS transistor. The silicide-encapsulation method of the present invention also results in silicidation of the exposed surfaces of the source and drain regions of the transistor with silicide. Devices produced according to the present invention may have different types of silicide formed on various gate and source/drain electrode surfaces. For example, devices produced according to the present invention may have different types of silicide formed on their gate and their source/drain electrodes.
The invention provides a method of fabricating a semiconductor device. The method includes providing a partially-formed electronic device including a semiconductor substrate having a gate dielectric and gate electrode formed thereon, and doped source and drain active regions on either side of the gate electrode. A silicide layer is formed on a top surface and sidewalls of the gate electrode and on the source and drain active regions, and spacer dielectric regions are formed between portions of the silicide layer on the gate electrode and the doped source and drain active regions, so that the gate electrode is isolated from the source and drain active regions.
In addition, the invention provides procedures for implementing the methods of fabricating a semiconductor devices which provide flexibility in the selection and placement of silicide materials.
Further, the invention provides a semiconductor device. The device includes a semiconductor substrate having an electrically active surface, a gate dielectric region provided on a portion of the electrically active surface of the substrate, a gate electrode having a top surface and two sidewall surfaces provided on the dielectric region, and doped source and drain active regions separated at the substrate's electrically active surface by a channel region under the gate dielectric region. A silicide layer is provided on the top surface and two sidewall surfaces of the gate electrode, and the doped source and drain active regions. Spacer dielectric regions are positioned between portions of the silicide layer on the gate electrode and the doped source and drain active regions, so that the spacer dielectric regions electrically isolate the gate electrode from the doped source and drain active regions.


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