Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-30
2001-07-10
Wilczewski, Mary (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S356000, C257S384000, C257S408000
Reexamination Certificate
active
06259140
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor devices which are protected from damage resulting from electrostatic discharge (ESD). More specifically, this invention relates to semiconductor devices having selectively silicided ESD transistors.
2. Description of Related Art
Gates of metal-oxide semiconductor (MOS) transistors receive input signals and transfer output signals in the form of a voltage. The gate oxide can break down if the applied voltage exceeds certain levels. Such excess voltages are often the result of human-operator or mechanical handling operations. Triboelectricity is an electrical charge which evolves when two materials are rubbed together. Human operators can create this type of electricity by walking across a room or by removing an integrated circuit (IC) from its plastic package. Triboelectricity results in high voltage, which when applied to a semiconductor device in the form of electrostatic discharge (ESD) can cause breakdown of the gate oxide or overheating due to overcurrent. This breakdown can cause immediate or expedited destruction of transistors and other devices.
In order to combat problems associated with ESD events, manufacturers of MOS devices design protection devices that provide paths through which to discharge nodes rapidly. Protection devices frequently include a transistor positioned between the input buffer or output buffer pads of a device and the respective gates to which the pads are connected. This transistor is often referred to as an ESD transistor. During an ESD event, a typical ESD transistor enters snap-back, a low resistance regime in which large amounts of current are conducted.
Certain processing enhancements, such as siliciding source/drain regions, increase the performance of small-dimension devices, but often negate the benefits of ESD transistors. These silicided regions are often positioned near the drain junction of the ESD transistors. The drain junction is a major source of heat during an ESD event. The proximity of the silicide to the drain junction frequently causes the silicide to melt during an ESD event which further causes breakdown of the semiconductor device.
One attempt to reduce the exposure of the silicide to heat has been to increase the gate-to-contact spacing in ESD transistors. However, this increased length adds resistance that impedes the current discharging through the ESD transistor. Thus, current tends to flow through other transistors on the semiconductor device before discharging through the ESD transistor. Accordingly, the increased resistance can negate the benefits of the protection device.
Another problem associated with silicided source/drain regions in a protection device is known as the “ballasting” effect. Due to the greatly reduced resistance of silicided regions during an ESD event, the current discharging through the ESD transistor may collapse into a thin filament. This collapse can lead to increased heating and premature device failure.
Many of the difficulties associated with silicide can be solved by selectively blocking silicide formation on the source, drain and/or gate electrode of the ESD transistors in semiconductor devices. Techniques for selective blocking of silicide formation frequently require two or more independent N+ implants, formation of multiple oxide layers and/or three or more masking steps. Multiple implants, oxide layer formations and maskings add to the costs and difficulty of semiconductor manufacture. Accordingly, there is a need for a process of creating semiconductor devices while reducing the number of N+ implants, oxide layer formation, and masking steps.
SUMMARY OF THE INVENTION
A method for forming a semiconductor device on a substrate having an ESD region and an internal region is disclosed. The method includes forming a protective layer over a portion of the ESD region which includes a gate electrode and then forming silicide on at least a portion of the internal region. The protective layer protects the portion of the ESD region from the formation of silicide. The method also includes removing a portion of the protective layer such that the remaining protective layer forms sidewall spacers on the gate electrode in the ESD region.
The provided method can also include forming a mask over portions of the ESD region and the internal region which are not protected by the protective layer after forming the silicide and then removing the mask concurrently with removing the portion of the protective layer.
Another embodiment of the method includes forming a protective layer over a portion of the ESD region and then forming silicide on at least a portion of the internal region. The protective layer protects the portion of the ESD region from the formation of silicide. The method also includes forming a mask on portions of the ESD region and the internal region which are not protected by the protective layer and removing the mask and a portion of the protective layer.
A semiconductor device manufactured by the above methods is also provided.
The methods can also include introducing N− type impurities into source/drain portions defined on the ESD and internal regions before forming the protective layer. Further, the methods can also include introducing additional N+ type impurities into source/drain portions defined on the ESD and internal regions after removing the portion of the protective layer.
Forming the protective layer can include forming an oxide layer over the ESD and internal regions and then forming a second mask on the oxide layer. The second mask on the oxide layer is formed over the portion of the ESD region to be protected from formation of silicide. Forming the protective layer can also include etching the mask and oxide layer to form the oxide layer into the protective layer. Etching the mask and oxide layers can form the oxide layer into spacers adjacent to a gate on the internal region.
REFERENCES:
patent: 4918811 (1990-04-01), Eichelberger
patent: 5262344 (1993-11-01), Mistry
patent: 5283449 (1994-02-01), Ooka
patent: 5342798 (1994-08-01), Huang
patent: 5516717 (1996-05-01), Hsu
patent: 5532178 (1996-07-01), Liaw et al.
patent: 5589423 (1996-12-01), White et al.
patent: 5619052 (1997-04-01), Chang et al.
patent: 5672527 (1997-09-01), Lee
patent: 5744839 (1998-04-01), Ma et al.
patent: 5834351 (1998-11-01), Chang et al.
patent: 5920774 (1999-07-01), Wu
patent: 6004838 (1999-12-01), Ma
patent: 6020242 (2000-02-01), Tsai et al.
patent: 6046087 (2000-04-01), Lin
patent: 6110771 (2000-08-01), Ahn
patent: 6121092 (2000-09-01), Liu
patent: 6156593 (2000-12-01), Peng
Anderson et al., “ESD protection for Mixed-Voltage I/O Using NMOS Transistors Stacked in a Cascade Configuration,” ESQ/ESD Symposium 98-61, pp. 2A.1.1.-2A.1.9.
Lai Cheng-Shang
Liu Meng-Hwang
Lu Tao-Cheng
Wang Mam-Tsung
Goodwin David
Haynes Mark A.
Haynes & Beffel LLP
Macronix International Co. Ltd.
Wilczewski Mary
LandOfFree
Silicide blocking process to form non-silicided regions on... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Silicide blocking process to form non-silicided regions on..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicide blocking process to form non-silicided regions on... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2473558