Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2001-08-22
2002-08-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C438S601000, C257S529000
Reexamination Certificate
active
06436738
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor fabrication and more specifically to fusible link devices.
BACKGROUND OF THE INVENTION
Fusible link devices (fuses) disposed on integrated circuit (IC) semiconductor substrates provide discretionary electrical connections and permit permanent information to be stored or permanent connections on the integrated circuit after it is manufactured. Conventional undoped fuses have larger and unstable pre-program issues while fully doped fuses have smaller post-program resistance issues.
U.S. Pat. No. 5,708,291 to Bohr et al. describes a fusible link device including a silicide layer over a polysilicon layer.
U.S. Pat. No. 5,814,876 to Peyre-Lavigne et al. describes a doped poly fuse.
U.S. Pat. No. 5,625,219 to Takagi describes a process for fabricating an ion implanted (I/I) anti-fuse.
U.S. Pat. No. 5,793,094 to Sanchez et al. describes a doped poly anti-fuse.
SUMMARY OF THE INVENTION
Accordingly, it is an object of an embodiment of the present invention to provide an improved method of fabricating a fusible link device.
Another object of an embodiment of the present invention is to provide an improved fusible link device.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a fusible link device comprises a poly layer having a center undoped portion and two doped end portions. The center undoped portion having a first resistance and the two doped end portions each having a second resistance that is lower than the first resistance. A silicide layer is formed over the poly layer with the silicide layer having a third resistance lower than the second resistance. The silicide layer agglomerating to form an electrical discontinuity within a discontinuity area in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased. The agglomeration of the silicide layer occurring over the center undoped portion of the poly layer. Contacts are electrically coupled to the two doped poly layer end portions for receiving the programming potential.
REFERENCES:
patent: 5585663 (1996-12-01), Bezema et al.
patent: 5625219 (1997-04-01), Takagi
patent: 5708291 (1998-01-01), Bohr et al.
patent: 5783467 (1998-07-01), Han et al.
patent: 5793094 (1998-08-01), Sanchez et al.
patent: 5814876 (1998-09-01), Peyre-Lavigne et al.
patent: 5821558 (1998-10-01), Han et al.
patent: 5854510 (1998-12-01), Sur, Jr. et al.
patent: 5882998 (1999-03-01), Sur, Jr. et al.
patent: 6368902 (2002-04-01), Kothandaraman et al.
Ackerman Stephen B.
Kennedy Jennifer M.
Niebling John F.
Saile George O.
Stanton Stephen G.
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