Semiconductor device manufacturing: process – Direct application of electrical current – To alter conductivity of fuse or antifuse element
Reexamination Certificate
1999-05-18
2001-07-10
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Direct application of electrical current
To alter conductivity of fuse or antifuse element
C438S131000, C438S132000
Reexamination Certificate
active
06258700
ABSTRACT:
RELATED APPLICATION
This application is related to U.S. patent application Ser. No. 08/537,147 entitled, “A Low Voltage, High Gain Fuse Sensing Circuit and Method”, filed Sep. 29, 1995.
FIELD OF THE INVENTION
The invention relates to the field of integrated circuit devices and more particularly, to fusible link devices in semiconductor integrated circuits.
BACKGROUND OF THE INVENTION
In integrated circuits including CMOS integrated circuits, it is often desirable to be able to permanently store information, or to form permanent connections on the integrated circuit after it is manufactured. Fuses or devices forming fusible links are frequently used for this purpose. Fuses can be used to program redundant elements to replace identical defective elements, for example. Fuses can also be used to store die identification or other such information, or to adjust the speed of a circuit by adjusting the resistance of the current path.
In some cases, electrically erasable programmable read only memory (EEPROM) devices are used to perform the discretionary connection function of a fuse device. Semiconductor process technologies continue to provide for smaller device geometries and operate at lower voltages. As the device geometries are reduced, so is the thickness of the gate oxide layer. EEPROM fuse devices require a relatively thick gate oxide to prevent high leakage currents and sustain a charge on the floating node. Thus, EEPROM fuse devices are not viable for use on many of the latest semiconductor process technologies.
Other fuse devices require an extra semiconductor processing step to form or program the discretionary connections. For example, one type of fuse device is “programmed” using a laser to open a link after the semiconductor device is processed and passivated. This type of fuse device not only requires an extra processing step to program or “blow” the fuse devices where desired, but also requires precise alignment of the laser on the fuse device to avoid destroying neighboring devices. This and other similar approaches can result in damage to the device passivation layer, and thus, lead to reliability concerns. In some approaches, the passivation layer must actually be removed before programming the fuse device to provide space for the fuse material when the connection is destroyed. In other approaches, where the passivation layer is not intentionally removed, the process of blowing the fuse can cause a hole in the passivation layer when the fuse material is displaced.
Another type of fuse device, referred to as an “oxide antifuse” device, is programmed using high voltages compared to the circuit's normal operating voltage supply. Therefore, the peripheral circuitry for these devices, generally requires higher junction breakdown voltages than those normally available on the integrated circuit. This is an issue for newer process technologies, and those in development, for the same reasons described above in reference to EEPROM fuse devices. The reduced gate oxide thicknesses require higher well doping which results in lower junction breakdown voltages, and thus, oxide antifuse devices may also not be viable for use with many of the latest process technologies.
The invention provides a small fuse device which can be manufactured without additional processing steps, and which can be reliably used with today's lower voltage, thinner gate oxide process technologies. Further, the fuse device of the invention can be programmed using relatively low voltages without damage to overlying dielectric layers.
SUMMARY OF THE INVENTION
A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections is described. The fusible link device of the invention has a first un-programmed resistance and includes a polysilicon layer and a silicide layer. The suicide layer is formed on the polysilicon layer, and agglomerates to form an electrical discontinuity in response to a predetermined programming potential being applied across the suicide layer, such that the resistance of the fusible link device can be selectively increased to a second programmed resistance.
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“Polysilicon Fuse Structure”;IBM Technical Disclosure Bulletin; vol. 29, No. 1, Jun. 1986; pp. 144-145.
Alavi Mohsen
Bohr Mark T.
Faatz Cynthia T.
Intel Corporation
Jr. Carl Whitehead
Vockrodt Jeff
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