Signature generator circuit

Details Signature generator circuit Signature generator circuit

1999-11-30

2001-10-09

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S093000, C326S037000, C327S141000

Reexamination Certificate

active

06300791

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits, and more specifically to a signature generator circuit for checking the validity of data.
2. Description of Related Art
The principle of integrated circuit transponders is to allow a reader to check the transponder and/or leave a trace in the transponder with minimum handling (it is enough for the transponder to be in the vicinity of a reader). Generally, the transponders are small-sized objects (credit card-sized badges, tags, or car keys) and they are not provided with an independent power source. To operate, the transponder is provided with a small antenna that picks up a modulated magnetic field. An integrated circuit connected to the two terminals of the antenna produces a supply voltage from this field and then demodulates and/or modulates the magnetic field to communicate with the reader.
Various problems arise in integrated circuits designed for use in transponders. The integrated circuits have to be small so that they can be placed in different objects without being destroyed by mechanical deformations of the object in which they are placed. Also, the consumption of the integrated circuits must be reduced to a minimum because the received supply does not make it possible to obtain a great deal of power. A greater problem arises in the transmission of data. Indeed, the data is modulated on a magnetic field that may be noise infested in varying degrees.
Furthermore, the constraints on size and consumption of the integrated circuit do not allow for a complicated error correction device. There are known ways of using a double check on parity. The double check on parity consists in checking the parity of each transmitted word and in checking a parity signature on a certain number of successively transmitted words. However, better error detection in transponder integrated circuits is desirable.
SUMMARY OF THE INVENTION
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide a small, low consumption signature generator circuit.
Another object of the present invention is to provide a signature generator circuit that is non-specific as to the number of words to be taken into account in a parity check. Thus, the circuit can produce a signature on a variable number of words.
One embodiment of the present invention provides a signature generator circuit for generator a signature word relating to a plurality of words. The signature generator circuit includes a logic gate that receives the plurality of words in series at one input, and a shift register that has a data input, a clock input, and a register output. The clock input receives a clock signal that sets the rate of the plurality of words, the data input is coupled to the output of the logic gate, and the register output is coupled to another input of the logic gate. In a preferred embodiment, the shift register also has a parallel output for outputting the contents of the shift register, and an asynchronous resetting input for resetting the contents of the shift register using a pulse.
Another embodiment of the present invention provides a method for generating a signature relating to a plurality of words using a logic gate and a shift register. According to the method, the contents of the shift register are reset. One of the words is supplied in series to the logic gate, at least one of the bits in the shift register is also supplied to the logic gate, and the output of the logic gate is stored in the shift register. The latter three steps are repeated for each of the words. In one preferred embodiment, the signature is retrieved from the shift register by outputting the contents of the shift register in parallel.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.


REFERENCES:
patent: 4216374 (1980-08-01), Lam et al.
patent: 4320509 (1982-03-01), Davidson
patent: 5167020 (1992-11-01), Kahn et al.
patent: 5228042 (1993-07-01), Gauthier et al.
patent: 5302866 (1994-04-01), Chiang et al.
patent: 0 805 575 (1997-11-01), None
patent: 2 062 042 (1981-05-01), None

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