Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Input noise margin enhancement
Patent
1994-07-14
1995-12-26
Westin, Edward P.
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Input noise margin enhancement
326 83, 327288, H03K 1716
Patent
active
054791111
ABSTRACT:
In a signal transmitting device in a semiconductor apparatus, a second signal 29 and a third signal 40 are activated by the activation of a first signal 2 which is entered. More specifically, the third signal 40 is firstly activated, and the second signal 29 is then activated while the third signal 40 is being activated, and then the third signal 40 is inactivated. Further, a fourth signal 42 is activated by the activation of the second signal 29 or by the activation of the third signal 40. Accordingly, even though a noise removing circuit 80 or the like is disposed in a first signal transmitting circuit 70 for activating the second signal 29, the period of time required by the time the fourth signal 42 is activated, can be shortened. Thus, there can be obtained a semiconductor apparatus which is fast in access (speed at which a signal is transmitted to a subsequent stage) and which is resistant to noise.
REFERENCES:
patent: 4596939 (1986-06-01), Yamada
patent: 4896056 (1990-06-01), Kunieda
patent: 4959562 (1990-09-01), Ootani
patent: 5184032 (1993-02-01), Leach
Matsushita Electronics Corporation
Sanders Andrew
Westin Edward P.
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