Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Patent
1996-12-24
1998-10-06
Westin, Edward
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
326 86, H03K 1716, H03K 190175
Patent
active
058182535
ABSTRACT:
A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission line itself. Each of the intra-block transmission line is provided with a resistance element having a resistance equal to or close to a value derived by subtracting a half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.
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"New I/O Proposal", Fujitsu, JEDEC JC16, San Diego, Dec. 5, 1993, pp. 1-12.
Kurihara Ryoichi
Takekuma Toshitsugu
Yamagiwa Akira
Hitachi , Ltd.
Roseen Richard
Westin Edward
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