Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol
Reexamination Certificate
1999-01-19
2001-10-16
Lefkowitz, Sumati (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Protocol
C710S011000, C710S014000, C710S071000, C710S120000, C710S120000
Reexamination Certificate
active
06304930
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an improved parallel signal transmission system operating with reduced power consumption.
A signal transmission system, including a transmitter unit, a receiver unit and a plurality of signal lines interposed between these units, is well known in the art. The total number of signal lines is prescribed based on the maximum amount of information to be transmitted. The transmitter unit includes a plurality of drivers each connected to associated one of the signal lines. For example, each of these drivers includes: a PMOS transistor interposed between a power line (voltage VDD) and an associated signal line; and an NMOS transistor interposed between the associated signal line and a ground line (voltage VSS).
High-speed signal transmission among a plurality of semiconductor integrated circuit chips mounted on a single printed wiring board is now in high demand. For example, in processing an enormous amount of moving picture data, a parallel signal transmission technique is employed to transmit address signals, data signals and other control signals between a memory controller and a memory. The higher the speed of signal transmission of this type is, the more noticeably a signal waveform is affected by reflection resulting from the inductance of a signal line. Thus, each of the signal lines used for parallel signal transmission is connected to a terminal voltage line (voltage VTT) via a low-impedance terminal resistor. The terminal voltage VTT is set approximately at (VDD+VSS)/2, for example.
Assume each of the signal lines used for parallel signal transmission among semiconductor integrated circuit chips is connected to a terminal resistor. Then, if the output of a driver is logic “1” (i.e., if the PMOS transistor in the driver is ON), direct current flows from the power line (voltage VDD) through the PMOS transistor and the associated signal line and terminal resistor into the terminal voltage line (voltage VTT). Conversely, if the output of a driver is logic “0” (i.e., if the NMOS transistor in the driver is ON), then direct current flows from the terminal voltage line (voltage VTT) through the associated terminal resistor and signal line and the NMOS transistor into the ground line (voltage VSS). All of these drivers and terminal resistors always generate these direct currents. Accordingly, the power consumed due to the generation of direct current is non-negligibly high.
In performing parallel signal transmission among circuit blocks in a single semiconductor integrated circuit chip, a signal line is not connected to a terminal resistor unlike chip-to-chip parallel transmission. Instead, direct current resulting from charging/discharging of parasitic capacitance associated with each signal line is always generated in every driver. Accordingly, the power consumed due to the generation of direct current is also non-negligibly high.
SUMMARY OF THE INVENTION
The object of the present invention is reducing the power consumed by such a parallel signal transmission system.
In a parallel signal transmission system in general, the amount of information to be transmitted per unit time is variable from moment to moment. A state where there is no information to be transmitted at all, e.g., a standby state, also exists. Moreover, in transmitting a multi-bit address signal, for example, a higher-order address signal is less variable than a lower-order address signal. In other words, a higher-order address signal can transmit a smaller amount of information per unit time than a lower-order address signal. The present invention was conceived by taking special note of these points. That is to say, according to the present invention, if the amount of information to be transmitted per unit time is relatively small, signal transmission is carried out using only one or some of the signal lines provided.
Specifically, according to the present invention, a signal line or lines to be used are selected on a mode-by-mode basis from a plurality of signal lines provided. For example, if a normal transmission mode has been specified, then parallel signal transmission is performed using all of these signal lines. Alternatively, if a limited transmission mode has been specified, then signal transmission is carried out without using at least one of the signal lines. In addition, in the limited transmission mode, the impedance between the non-used signal line and a direct current power supply is increased in such a manner as to reduce the current flowing through the non-used signal line. Furthermore, if a transmission stop mode has been specified, the impedances between the respective signal lines and the direct current power supply are all increased such that none of these signal lines are used for signal transmission and that the currents flowing through these signal lines are all reduced. In order to increase the impedance between a signal line and the direct current power supply, the output impedance of a driver implemented as a CMOS inverter may be increased by turning OFF PMOS and NMOS transistors in the driver.
More specifically, the signal transmission system according to the present invention includes: a transmitter unit; a receiver unit; and a plurality of signal lines interposed between these units. The transmitter unit includes: a plurality of drivers each connected to associated one of the signal lines; and logic means. If a normal transmission mode has been specified, then the logic means activates all of these drivers such that parallel signal transmission is performed using all of these signal lines. On the other hand, if a limited transmission mode has been specified, the logic means activates used one or ones of the drivers and increases the output impedance of non-used one of drivers such that signal transmission is performed without using at least one of the signal lines. In the limited transmission mode, the non-used driver having high output impedance reduces the direct current flowing through the associated non-used signal line. The receiver unit also includes logic means correspondingly. If the normal transmission mode has been specified, then the logic means of the receiver unit validates all signals received from the signal lines. Conversely, if the limited transmission mode has been specified, then the logic means of the receiver unit validates a signal or signals received from used one or ones of the signal lines and invalidates a signal received from the non-used one of the signal lines. According to the present invention, a transmission stop mode may be employed in addition to the normal transmission and limited transmission modes. In the transmission stop mode, the logic means of the transmitter unit increases all the output impedances of the respective drivers, while the logic means of the receiver unit invalidates all the signals received from the signal lines.
In order to perform signal transmission using a reduced number of signal lines in the limited transmission mode as in the normal transmission mode, parallel/serial converter and serial/parallel converter are provided as the logic means of the transmitter and receiver units, respectively.
REFERENCES:
patent: 4463421 (1984-07-01), Laws
patent: 4680754 (1987-07-01), Fechalos
patent: 4799216 (1989-01-01), Johnson et al.
patent: 5742531 (1998-04-01), Freidin et al.
patent: 6021450 (2000-02-01), Yoshizawa et al.
patent: 7-235952 (1995-09-01), None
Lefkowitz Sumati
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Robinson Eric J.
LandOfFree
Signal transmission system having multiple transmission modes does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Signal transmission system having multiple transmission modes, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal transmission system having multiple transmission modes will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2553975