Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2001-08-08
2002-07-23
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S088000
Reexamination Certificate
active
06424188
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal transmission device that transmits signals fed thereto to another device through a transformer.
2. Description of the Prior Art
As an example of a conventional signal transmission device, a terminal adapter, which is needed to connect terminal equipment such as a personal computer to an ISDN (integrated services digital network) line, will be described.
FIG. 4
is a diagram showing an outline of an example of a configuration that permits connection between an ISDN line and terminal equipment. A similar configuration is disclosed in Japanese Patent Application Laid-Open No. H11-330937.
As shown in this figure, to connect terminal equipment TE to an ISDN line, it is necessary to use a terminal adapter
10
that converts the signals fed thereto from the terminal equipment TE into a signal format adapted for the ISDN line and a digital service unit
20
(hereinafter referred to as the “DSU
20
”) that serves as a terminal interface device by converting the signals from a telephone company, which are adapted for network transfer, to signals adapted for distribution inside a household so as to be ready for bus-based wiring.
The interface I/F between the terminal adapter
10
and the DSU
20
is composed of a transformer employing coils, and the ISDN standard sets strict requirements regarding overshoots and undershoots that occur at such a signal conversion point.
FIG. 5
is a diagram showing an outline of the configuration of an example of a conventional terminal adapter
10
. A logic circuit
11
that converts the signals from the terminal equipment TE into a signal format adapted for the ISDN line is connected through an output circuit
12
to the primary coil L
1
of the interface I/F. The output circuit
12
feeds the coil L
1
with current based on the signals output from the logic circuit
11
, and the output stage of the output circuit
12
is composed of a P-channel MOS transistor QH
1
and an N-channel MOS transistor QL
1
that are connected in series between a supply voltage line and a GND (ground) line and a P-channel MOS transistor QH
2
and an N-channel MOS transistor QL
2
that are similarly connected in series between the supply voltage line and the GND line.
The drains of the transistors QH
1
and QL
1
are connected together through a resistor R
1
to one end of the coil L
1
, and the drains of the transistors QH
2
and QL
2
are connected together through a resistor R
2
to the other end of the coil L
1
. The sources of the transistors QH
1
and QH
2
are connected through constant-current source circuits CC
1
and CC
2
, respectively, to the supply voltage line, and the sources of the transistors QL
1
and QL
2
are connected to the GND line. The resistors R
1
and R
2
both serve to limit the current that flows through the coil L
1
, and the constant-current source circuits CC
1
and CC
2
both serve to limit transient fluctuations in the current that flows through the coil L
1
.
The gate of the transistor QH
1
is connected directly to a first output terminal O
1
of the logic circuit
11
, and the gate of the transistor QH
2
is connected directly to a second output terminal O
2
of the logic circuit
11
. The gate of the transistor QL
1
is connected through a timing adjustment circuit T
1
to the first output terminal O
1
, and the gate of the transistor QL
2
is connected through a timing adjustment circuit T
2
to the second output terminal O
2
.
Here, when the logic circuit
11
outputs at its first and second output terminals O
1
and O
2
a H (high) level and a L (low) level, respectively, the transistors QH
1
and QL
2
are off, and the transistors QL
1
and QH
2
are on. Accordingly, the constant current produced by the constant-current source circuit CC
2
flows through the transistor QH
2
, resistor R
2
, coil L
1
, resistor R
1
, and transistor QL
1
to the GND line, and thus the voltage F appearing across the coil L
2
is positive (in a H state).
By contrast, when the logic circuit
11
outputs at its first and second output terminals O
1
and O
2
a L level and a H level, respectively, the transistors QH
1
and QL
2
are on, and the transistors QL
1
and QH
2
are off. Accordingly, the constant current produced by the constant-current source circuit CC
1
flows through the transistor QH
1
, resistor R
1
, coil L
1
, resistor R
2
, and transistor QL
2
to the GND line, and thus the voltage F appearing across the coil L
2
is negative (in a L state).
When the logic circuit
11
outputs a L level at both of its first and second output terminals O
1
and O
2
, no current flows through the coil L
1
, and thus no voltage appears across the coil L
2
(in a M (middle) state). It never occurs that the logic circuit
11
outputs a H level at both of its first and second output terminals O
1
and O
2
.
Now, the operation of the timing adjustment circuits T
1
and T
2
mentioned above will be described. The timing adjustment circuits T
1
and T
2
are provided for the purpose of reducing the overshoots and undershoots that occur in the square wave appearing across the coil L
1
. The timing adjustment circuits T
1
and T
2
are so configured that, when the input thereto rises to a H level, they turn their output to a H level irrespective of a clock CLK but, when the input drops to a L level, they turn their output to a L level after counting a predetermined number of pulses in the clock CLK.
For example, in a case where the timing adjustment circuits T
1
and T
2
receive, as their clock CLK, the clock signal (for example, having a frequency of 6 MHz) used for the logic circuit
11
, and are so configured that they turn their output to a L level in synchronism with the second rising edge in the clock CLK, the timing adjustment circuits T
1
and T
2
produce a delay time t of about 170 nanoseconds.
In this way, the timing adjustment circuits T
1
and T
2
serve to shift level switching points of the digital signals that are applied to the gates of the transistors QL
1
and QL
2
, and desired timing adjustment can easily be achieved by using, for example, flip-flops. Thus, it is possible to produce a short delay stably, without slowing down the data transfer rate.
FIG. 6
is a timing chart showing the waveforms of signals observed at relevant points in the terminal adapter
10
. In this figure, reference symbols A, B, C, and D indicate the digital signals that are applied to the gates of the transistors QH
1
, QL
1
, QH
2
, and QL
2
, respectively, and reference symbol F indicates the voltage that appears across the coil L
2
.
As described previously, in the terminal adapter
10
configured as described above, as shown in the figure, level switching points of the digital signals B and D applied to the gates of the corresponding transistors are shifted by the timing adjustment circuits T
1
and T
2
. More precisely, when the individual transistors are switched between on and off, any transistor that has been receiving current from the coil L
1
up to that moment is switched from on to off with a delay of t from the time point at which the other transistors are switched between on and off.
In the terminal adapter
10
configured as described above, it is possible, indeed, to reduce transient fluctuations in the current flowing through the coil L
1
and thereby reduce the back electromotive force induced by the inductance of the coil. As a result, it is possible to reduce the overshoots OS and undershoots US (indicated by a dash-and-dot line in the figure) that occur in the square wave appearing across the coil L
2
.
However, in the terminal adapter
10
configured as described above, on occasions when the levels of the two signals output from the logic circuit
11
are switched in opposite directions, i.e. when one signal turns from a H level to a L level and simultaneously the other signal turns from a L level to a H level, the square wave appearing across the coil L
2
may be distorted as indicated by reference symbol S in FIG.
6
. This problem arises when the del
Arent Fox Kintner & Plotkin & Kahn, PLLC
Callahan Timothy P.
Nguyen Linh
Rohm & Co., Ltd.
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