Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2000-12-13
2002-07-30
Le, Don Phu (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S093000, C326S086000
Reexamination Certificate
active
06426654
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal transmission circuit placed on a CMOS semiconductor integrated circuit chip, and particularly to a circuit for transmitting a signal over long-distance sections at high speed.
2. Description of the Related Art
A technique capable of, when a long-distance signal line is caused to transmit a signal within a semiconductor integrated circuit chip, dividing the signal line every suitable lengths and providing buffers to thereby control an increase in delay time due to the resistance of the signal line has been disclosed in Japanese Published Unexamined Patent Application No. Hei 06-334042.
An example in which a bus, which performs a dynamic operation, is divided to provide relaying means, has been disclosed in U.S. Pat. No. 4,883,989. This example will be explained with reference to
FIG. 15. A
first bus
12
is connected to a gate of an N channel type MOS transistor (hereinafter called “NMOS transistor”) through a CMOS inverter
16
. A P channel type MOS transistor (hereinafter called “PMOS transistor”)
19
to which a clock identical to a clock &phgr; for precharge of the first bus is applied, is connected in tandem with the NMOS transistor
17
, and a second bus
13
is connected to its connecting node. Thus, a change in the potential of the first bus
12
subsequent to the precharge of the first bus
12
appears similarly even in the case of the second bus
13
, and signal transmission is carried out. Incidentally, the transmission of a signal from the second bus
12
to the first bus
13
can also be implemented by a connecting circuit similar to above, which comprises a CMOS inverter
18
, and a cascade circuit of a PMOS transistor
14
and an NMOS transistor
19
.
Incidentally, the disclosure of U.S. Ser. No. 09/599,738 corresponding to the prior application assigned by the same assignee as the present application is related to the present application except for the above-descried example known per se in the art.
SUMMARY OF THE INVENTION
As in the prior art example disclosed in Japanese Published Unexamined Patent Application No. Hei 06-334042 referred to above, the delay time developed due to the resistance of the signal line can be shortened where the long-distance signal line is divided to interpose the buffers therein. However, a delay time associated with the passage of the signal through each buffer is developed as alternated. Thus, it is useful to divide, every suitable lengths, such an extremely long signal line that the delay time developed due to the resistance of the signal line becomes greater than the delay time developed due to each buffer and provide the buffers. However, if the signal line is divided short so that the delay time developed due to the resistance of the signal line becomes nearly equal to or less than the delay time developed due to the buffer, then the time necessary for the signal transmission becomes long in reverse.
In the structure disclosed in U.S. Pat. No. 4,883,989, the signal passes through the active elements of two stages comprised of the inverter and NMOS transistor until it is transmitted from the first bus to the second bus. Thus, the relaying means provides a large delay time for the signal as compared with the buffers disclosed in Japanese Published Unexamined Patent Application No. Hei 06-334042 referred to above.
Therefore, one object of the present invention is to provide a signal transmission circuit capable of transmitting a signal over a relatively long distance on a semiconductor integrated circuit chip in a shorter delay time.
Another object of the present invention is to decrease the number of active elements such as MOS transistors or the like interposed in a signal transmission path and reduce a total gate width of these elements necessary for signal transmission to thereby contribute to high integration of a semiconductor integrated circuit.
A signal transmission circuit of the present invention is basically a dynamic circuit. That is, a signal line for signal transmission is periodically precharged to a specific potential (first potential) by elements for precharge and is driven to another potential (second potential) by driving elements according to the level of an input signal.
A typical embodiment disclosed by the present application is characterized in that elements for precharge are respectively connected to a single signal line, i.e., a continuous signal line with no buffers or active elements for relay interposed in the way thereof, at three or more places. Described more specifically, a plurality of elements for precharge are respectively connected to the signal line at a start or leading point of the single signal line, i.e., a position near a connecting point from an element for driving the signal line, an end thereof, i.e., a position near a connecting point to the next-stage element for the signal line, and a position located between these.
According to the present structure, since each individual precharge elements precharge the signal line under their sharing even in the case of the transmission of a signal over a relatively long distance, it is possible to avoid a delay in precharge operation due to the resistance of the signal line. As a result, high-speed signal transmission is allowed.
A characteristic of another embodiment disclosed by the present application resides in that relaying elements are interposed in plural places lying in the course of a signal transmission circuit. That is, a signal path includes a plurality of signal line sections partitioned by these relaying elements. Described more specifically, the signal path is configured in such a manner that a first type of signal line section precharged to a first potential and having a positive operation for driving it to a second potential, and a second type of signal line section precharged to the second potential in reverse and having a negative operation for driving it to the first potential are placed alternately from the upstream side to the downstream side. A relaying element from the first type of signal line section to the second type of signal line section is an active element for driving a signal line of a subsequent stage to the first potential according to the driving of a signal line of a preceding stage to the second potential. Each of the second type of signal lines is an active element for driving a signal line of a subsequent stage to the first potential according to the driving a signal line of a preceding stage to the second potential. These active elements are typified by MOS transistors.
Elements for precharge are connected even to each individuals of these plural signal line sections at their plural places.
Even in the case of such a structure, avoidance of a delay in precharge operation can be achieved owing the above sharing of precharge. Further, since each of the relaying elements interposed in the signal transmission path is one active element, a transmission delay can be reduced as compared with the prior art example in which the active elements of the two stages relay the signal line sections.
REFERENCES:
patent: 4883989 (1989-11-01), Mizukami
patent: 6157204 (2000-12-01), Sher et al.
patent: 6240035 (2001-05-01), Noda et al.
patent: 6249147 (2001-06-01), Vinh et al.
patent: 6334042 (1994-12-01), None
Hitachi , Ltd.
Le Don Phu
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