Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-06-23
2002-01-08
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S086000, C326S030000, C326S098000, C326S093000
Reexamination Certificate
active
06337581
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a transmission circuit for transmitting signals between circuit units on a semiconductor integrated circuit, and a semiconductor memory using the same.
BACKGROUND OF THE INVENTION
A transmission circuit capable of transmitting signals at high speed even through a wire long in length and large in parasitic capacitance has been desired for a semiconductor integrated circuit. In the case of a CMOS circuit, a circuit shown in
FIG. 18
is known as a conventional transmission circuit. In the same drawing, reference numeral
101
indicates a dynamic CMOS circuit used as a driver circuit. Symbol W indicates an equivalent circuit of a wire in which a parasitic capacitance CL and a parasitic resistance RL are taken into consideration. Reference numeral
200
indicates an inverter used as a receiving circuit. Symbol &phgr;
1
indicates a control signal and Symbol IN indicates a data signal respectively. Operational waveforms of the circuit are illustrated in FIG.
19
. When the control signal &phgr;
1
is a low potential VSS (‘L’), a precharge period is set up, whereas when the control signal &phgr;
1
is a high potential VDD (‘H’), an evaluation period is setup. During the precharge period, an output Q
1
produced from the driver circuit
101
reaches ‘H’. If the data signal IN is ‘H’ (indicated by a solid line) when the control signal &phgr;
1
changes from ‘L’ to ‘H’, then the output Q
1
is discharged and changed from ‘H’ to ‘L’. Under the influence of a time interval (CR time constant) obtained from the product of the parasitic capacitance CL and the parasitic resistance RL of the wire W, an output Q
1
B at the exit of the wire W changes from ‘H’ to ‘L’. Thereafter, the receiving circuit
201
outputs an output Q
2
in response to the output Q
1
B at the exit of the wire W. On the other hand, if the data signal IN is ‘L’ (indicated by a broken line) when the control signal &phgr;
1
changes from ‘L’ to ‘H’, then no outputs Q
1
and Q
1
B are discharged and they are maintained at ‘H’. As the parasitic capacitance of the output part Q
1
increases, transistors large in gate width are used as transistors for the driver circuit
101
, and the shortening of the time required to charge and discharge the output Q
1
is achieved.
SUMMARY OF THE INVENTION
In the conventional transmission circuit as indicated by the operational waveforms shown in
FIG. 19
, the time necessary for the output Q
1
of the driver circuit
101
to fall is faster and a delay time (tpd
1
) thereof is small. However, the waveform is rendered dull due to the influence of the parasitic capacitance and the parasitic resistance at the exit Q
1
B of the wire W, and a delay time (tcrf) is developed (where the logic threshold potential of the inverter constituting the receiving circuit is supposed to be a common (VDD/2)). The delay time developed due to the influence of the wire increases in proportion to the product of the parasitic capacitance and the parasitic resistance. Therefore, the delay time is so long and becomes dominant when the wire is long, and hence the performance of the semiconductor integrated circuit is rate-controlled by the delay time developed under the influence of the wire.
Incidentally, a waveform-dull phenomenon is not limited only to the case where the length of the wire is long. There may be cases in which transistors each having a small gate width, which are short in wiring length and large in parasitic capacity, are used for the driver circuit
101
.
With the foregoing problems in view, it is therefore an object of the present invention to shorten the time required to transmit a data signal even when a signal waveform is made dull.
Another object of the present invention is to shorten a precharge time at an exit portion of a signal wire (transmission line) and shorten a transmission cycle time.
According to one aspect of the present invention, for achieving the above objects, there is provided a transmission circuit, comprising a driver circuit alternately controlled to a precharge period and an evaluation period according to a first control signal, the driver circuit precharging an output node to a first source potential during the precharge period and driving the output node to either one of the first source potential and a second source potential according to a potential at an input node during the evaluation period, a signal line coupled to the output node of the driver circuit so as to be driven by the driver circuit, and a receiving circuit comprising a semiconductor logic circuit, which has a first node and a second node and is alternately controlled to the precharge period and the evaluation period according to a second control signal to precharge the first and second nodes to the first source potential together during the precharge period, and discharge the second node according to a potential at the first node and discharge the first node according to a potential on the signal line during the evaluation period, thereby making a distinction as to the potential on the signal line with the potential at the first node as a reference potential. Further a signal line precharge transistor is provided at an exit portion of the signal line (transmission line).
REFERENCES:
patent: 5291876 (1994-03-01), Bridges et al.
patent: 5373203 (1994-12-01), Nicholes et al.
patent: 5859548 (1999-01-01), Kong
patent: 6043674 (2000-03-01), Sobelman
patent: 6043696 (2000-03-01), Klass et al.
patent: 6104209 (2000-08-01), Keeth et al.
patent: 6108805 (2000-08-01), Rajsuman
patent: 10150358 (1998-01-01), None
Arakawa Fumihiko
Kanetani Kazuo
Kusunoki Takeshi
Nambu Hiroaki
Yamasaki Kaname
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Tan Vibol
Tokar Michael
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